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Searched refs:RD4 (Results 1 – 25 of 85) sorted by relevance

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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c325 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_pex_enable()
580 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
584 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
588 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
596 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in uphy_pex_enable()
603 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
609 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
613 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
[all …]
H A Dtegra210_pmc.c203 RD4(struct tegra210_pmc_softc *sc, bus_size_t r) in RD4() function
227 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); in tegra210_pmc_set_powergate()
234 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
247 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
287 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
295 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
310 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
505 orig = RD4(sc, PMC_SCRATCH0); in tegra210_pmc_check_secure()
507 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure()
[all …]
H A Dtegra210_clk_pll.c603 RD4(sc, sc->base_reg, &reg); in pll_enable()
616 RD4(sc, sc->base_reg, &reg); in pll_disable()
688 RD4(sc, sc->base_reg, &val); in get_divisors()
714 RD4(sc, sc->misc_reg, &reg); in is_locked()
719 RD4(sc, sc->misc_reg, &reg); in is_locked()
724 RD4(sc, sc->base_reg, &reg); in is_locked()
758 RD4(sc, sc->base_reg, &reg); in plle_enable()
763 RD4(sc, PLLE_AUX, &reg); in plle_enable()
769 RD4(sc, sc->misc_reg, &reg); in plle_enable()
779 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_efuse.c50 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (FUSES_START + (_r))) macro
194 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO); in tegra124_init()
195 sku->soc_iddq_value = RD4(sc, TEGRA124_FUSE_SOC_IDDQ); in tegra124_init()
196 sku->cpu_iddq_value = RD4(sc, TEGRA124_FUSE_CPU_IDDQ); in tegra124_init()
197 sku->gpu_iddq_value = RD4(sc, TEGRA124_FUSE_GPU_IDDQ); in tegra124_init()
198 sku->soc_speedo_value = RD4(sc, TEGRA124_FUSE_SOC_SPEEDO_0); in tegra124_init()
199 sku->cpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_0); in tegra124_init()
200 sku->gpu_speedo_value = RD4(sc, TEGRA124_FUSE_CPU_SPEEDO_2); in tegra124_init()
284 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4); in tegra210_get_speedo_revision()
286 reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4); in tegra210_get_speedo_revision()
[all …]
H A Dtegra_usbphy.c306 #define RD4(sc, offs) \ macro
318 if ((RD4(sc, reg) & mask) == val) in reg_wait()
331 val = RD4(sc, CTRL_USB_HOSTPC1_DEVLC); in usbphy_utmi_phy_clk()
354 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
358 val = RD4(sc, UTMIP_TX_CFG0); in usbphy_utmi_enable()
362 val = RD4(sc, UTMIP_HSRX_CFG0); in usbphy_utmi_enable()
369 val = RD4(sc, UTMIP_HSRX_CFG1); in usbphy_utmi_enable()
374 val = RD4(sc, UTMIP_DEBOUNCE_CFG0); in usbphy_utmi_enable()
379 val = RD4(sc, UTMIP_MISC_CFG0); in usbphy_utmi_enable()
384 val = RD4(sc,IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
[all …]
H A Dtegra_soctherm.c132 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
521 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); in soctherm_init_tsensor()
540 val = RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0); in soctherm_init_tsensor()
546 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), in soctherm_init_tsensor()
547 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), in soctherm_init_tsensor()
548 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), in soctherm_init_tsensor()
549 RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), in soctherm_init_tsensor()
550 RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), in soctherm_init_tsensor()
551 RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) in soctherm_init_tsensor()
578 val = RD4(sc, sensor->sensor_base + TSENSOR_STATUS1); in soctherm_read_temp()
[all …]
H A Dtegra_i2c.c192 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
242 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
248 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
290 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_bus_clear()
296 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); in tegra_i2c_bus_clear()
301 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & in tegra_i2c_bus_clear()
309 status = RD4(sc, I2C_BUS_CLEAR_STATUS); in tegra_i2c_bus_clear()
344 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_hw_init()
365 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_tx()
391 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_rx()
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c233 RD4(struct bcm_sdhost_softc *sc, bus_size_t off) in RD4() function
255 val = RD4(sc, off & ~3); in RD2()
266 val = RD4(sc, off & ~3); in RD1()
276 val32 = RD4(sc, off & ~3); in WR2()
287 val32 = RD4(sc, off & ~3); in WR1()
302 RD4(sc, HC_COMMAND)); in bcm_sdhost_print_regs()
304 RD4(sc, HC_ARGUMENT)); in bcm_sdhost_print_regs()
306 RD4(sc, HC_TIMEOUTCOUNTER)); in bcm_sdhost_print_regs()
308 RD4(sc, HC_CLOCKDIVISOR)); in bcm_sdhost_print_regs()
310 RD4(sc, HC_RESPONSE_0)); in bcm_sdhost_print_regs()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) in RD4() function
177 reg = RD4(sc, CCM_CGPR); in ccm_attach()
180 reg = RD4(sc, CCM_CLPCR); in ccm_attach()
224 reg = RD4(sc, CCM_CSCMR1); in imx_ccm_ssi_configure()
239 reg = RD4(sc, CCM_CS1CDR); in imx_ccm_ssi_configure()
253 reg = RD4(sc, CCM_CS2CDR); in imx_ccm_ssi_configure()
271 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); in imx_ccm_usb_enable()
325 WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA); in imx6_ccm_sata_enable()
328 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); in imx6_ccm_sata_enable()
333 if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) & in imx6_ccm_sata_enable()
[all …]
H A Dimx6_snvs.c80 RD4(struct snvs_softc *sc, bus_size_t offset) in RD4() function
106 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) in snvs_rtc_enable()
119 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { in snvs_gettime()
131 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
132 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
133 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
134 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c56 #define RD4 (sc->read) macro
292 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) in sdhci_fsl_fdt_get_clock()
294 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) in sdhci_fsl_fdt_get_clock()
322 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); in fsl_sdhc_fdt_set_clock()
385 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); in sdhci_fsl_fdt_read_1()
399 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); in sdhci_fsl_fdt_read_1()
414 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); in sdhci_fsl_fdt_read_2()
424 val32 = RD4(sc, SDHCI_INT_STATUS); in sdhci_fsl_fdt_read_2()
425 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); in sdhci_fsl_fdt_read_2()
428 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); in sdhci_fsl_fdt_read_2()
[all …]
H A Dfsl_sdhci.c190 RD4(struct fsl_sdhci_softc *sc, bus_size_t off) in RD4() function
215 wrk32 = RD4(sc, SDHC_PROT_CTRL); in fsl_sdhci_read_1()
254 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); in fsl_sdhci_read_1()
276 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); in fsl_sdhci_read_2()
298 val32 = RD4(sc, SDHCI_INT_STATUS); in fsl_sdhci_read_2()
299 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); in fsl_sdhci_read_2()
311 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); in fsl_sdhci_read_2()
320 val32 = RD4(sc, off); in fsl_sdhci_read_4()
388 val32 = RD4(sc, SDHC_PROT_CTRL); in fsl_sdhci_write_1()
412 val32 = RD4(sc, off & ~3); in fsl_sdhci_write_1()
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c171 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
368 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
377 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); in usb3_port_init()
389 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
394 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
399 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
413 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); in pcie_powerup()
418 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); in pcie_powerup()
425 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); in pcie_powerup()
431 reg = RD4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); in pcie_powerup()
[all …]
H A Dtegra124_clk_pll.c417 RD4(sc, sc->base_reg, &reg); in pll_enable()
430 RD4(sc, sc->base_reg, &reg); in pll_disable()
495 RD4(sc, sc->base_reg, &val); in get_divisors()
521 RD4(sc, sc->misc_reg, &reg); in is_locked()
526 RD4(sc, sc->misc_reg, &reg); in is_locked()
531 RD4(sc, sc->base_reg, &reg); in is_locked()
566 RD4(sc, sc->base_reg, &reg); in plle_enable()
570 RD4(sc, PLLE_AUX, &reg); in plle_enable()
576 RD4(sc, sc->misc_reg, &reg); in plle_enable()
586 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
[all …]
H A Dtegra124_pmc.c136 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
191 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); in tegra124_pmc_set_powergate()
198 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
211 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
238 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
251 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
259 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
512 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
517 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
[all …]
/freebsd/sys/dev/cadence/
H A Dif_cgem.c220 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
251 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); in cgem_get_mac()
252 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff; in cgem_get_mac()
384 queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) & in cgem_null_qs()
881 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT); in cgem_poll_hw_stats()
882 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32; in cgem_poll_hw_stats()
884 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX); in cgem_poll_hw_stats()
885 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX); in cgem_poll_hw_stats()
886 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX); in cgem_poll_hw_stats()
887 sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX); in cgem_poll_hw_stats()
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.c73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
137 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); in zy7_slcr_cpu_reset()
271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_source()
297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_source()
361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_freq()
410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_freq()
490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); in zy7_pl_fclk_enabled()
507 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); in zy7_pl_level_shifters_enabled()
596 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); in zy7_slcr_attach()
601 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); in zy7_slcr_attach()
[all …]
H A Duart_dev_cdnc.c54 #define RD4(bas, reg) \ macro
333 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
351 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_rxready()
365 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_getc()
372 c = RD4(bas, CDNC_UART_FIFO); in cdnc_uart_getc()
493 modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) & in cdnc_uart_bus_setsig()
515 status = RD4(bas, CDNC_UART_ISTAT_REG); in cdnc_uart_bus_receive()
525 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_bus_receive()
527 c = RD4(bas, CDNC_UART_FIFO) & 0xff; in cdnc_uart_bus_receive()
[all …]
H A Dzy7_gpio.c182 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro
298 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { in zy7_gpio_pin_getflags()
300 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) in zy7_gpio_pin_getflags()
327 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); in zy7_gpio_pin_setflags()
331 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & in zy7_gpio_pin_setflags()
335 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | in zy7_gpio_pin_setflags()
340 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
342 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
381 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; in zy7_gpio_pin_get()
398 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); in zy7_gpio_pin_toggle()
/freebsd/sys/dev/eqos/
H A Dif_eqos.c97 #define RD4(sc, o) bus_read_4(sc->res[EQOS_RES_MEM], (o)) macro
127 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_readreg()
129 val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; in eqos_miibus_readreg()
161 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_writereg()
188 reg = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_miibus_statchg()
422 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); in eqos_setup_rxfilter()
464 val = RD4(sc, GMAC_DMA_MODE); in eqos_reset()
511 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); in eqos_init()
517 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); in eqos_init()
523 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); in eqos_init()
[all …]
/freebsd/sys/arm/mv/clk/
H A Da37x0_tbg_pll.c42 #define RD4(_clk, offset, val) \ macro
61 RD4(clk, sc->tbg_bypass.offset, &val); in a37x0_tbg_pll_recalc_freq()
65 RD4(clk, sc->vcodiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
68 RD4(clk, sc->refdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
71 RD4(clk, sc->fbdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
/freebsd/sys/arm/mv/
H A Dmv_thermal.c121 #define RD4(sc, reg) \ macro
142 reg = RD4(sc, STATUS); in mv_thermal_wait_sensor()
163 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
185 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
202 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; in mv_thermal_read_sensor()
221 reg = RD4(sc, CONTROL0); in ap806_init()
241 reg = RD4(sc, CONTROL1); in cp110_init()
247 reg = RD4(sc, CONTROL0); in cp110_init()
/freebsd/sys/dev/ffec/
H A Dif_ffec.c225 RD4(struct ffec_softc *sc, bus_size_t off) in RD4()
311 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) in ffec_miibus_iowait()
337 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; in ffec_miibus_readreg()
388 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; in ffec_miibus_statchg()
389 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | in ffec_miibus_statchg()
391 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; in ffec_miibus_statchg()
483 mibc = RD4(sc, FEC_MIBC_REG); in ffec_clear_stats()
530 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); in ffec_harvest_stats()
531 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); in ffec_harvest_stats()
533 RD4(s in ffec_harvest_stats()
224 RD4(struct ffec_softc *sc, bus_size_t off) RD4() function
[all...]
/freebsd/sys/arm64/broadcom/genet/
H A Dif_genet.c80 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_MAC], (reg)) macro
264 major = (RD4(sc, GENET_SYS_REV_CTRL) & REV_MAJOR) >> REV_MAJOR_SHIFT; in gen_attach()
270 minor = (RD4(sc, GENET_SYS_REV_CTRL) & REV_MINOR) >> REV_MINOR_SHIFT; in gen_attach()
272 RD4(sc, GENET_SYS_REV_CTRL) & REV_PHY); in gen_attach()
465 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL); in gen_get_eaddr()
467 maclo = htobe32(RD4(sc, GENET_UMAC_MAC0)); in gen_get_eaddr()
468 machi = htobe16(RD4(sc, GENET_UMAC_MAC1) & 0xffff); in gen_get_eaddr()
492 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL); in gen_reset()
522 val = RD4(sc, GENET_RBUF_CTRL); in gen_enable()
529 val = RD4(sc, GENET_UMAC_CMD); in gen_enable()
[all …]
/freebsd/sys/dev/tpm/
H A Dtpm_tis.c

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