| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx_wdog.c | 87 RD2(struct imx_wdog_softc *sc, bus_size_t offs) in RD2() function
111 reg = RD2(sc, WDOG_CR_REG); in imx_wdog_enable()
122 reg = RD2(sc, WDOG_MCR_REG); in imx_wdog_enable()
206 WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG)); in imx_wdog_attach()
217 if (RD2(sc, WDOG_MCR_REG) & WDOG_MCR_PDE) in imx_wdog_attach()
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| /freebsd/sys/dev/sdhci/ |
| H A D | sdhci.c | 82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) macro
231 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); in sdhci_dumpregs_buf()
233 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); in sdhci_dumpregs_buf()
235 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); in sdhci_dumpregs_buf()
241 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs_buf()
247 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs_buf()
253 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); in sdhci_dumpregs_buf()
423 clk = RD2(slot, SDHCI_CLOCK_CONTROL); in sdhci_set_clock()
432 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & in sdhci_set_clock()
492 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) in sdhci_set_clock()
[all …]
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| /freebsd/sys/dev/iicbus/controller/cadence/ |
| H A D | cdnc_i2c.c | 111 #define RD2(sc, off) (bus_read_2((sc)->mem_res, (off))) macro
310 status = RD2(sc, CDNC_I2C_ISR) & ~RD2(sc, CDNC_I2C_IMR); in cdnc_i2c_intr()
393 statr = RD2(sc, CDNC_I2C_SR); in cdnc_i2c_xfer_rd()
398 msg->buf[idx++] = RD2(sc, CDNC_I2C_DATA); in cdnc_i2c_xfer_rd()
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| /freebsd/sys/dev/ffec/ |
| H A D | if_ffec.c | 211 RD2(struct ffec_softc *sc, bus_size_t off) in RD2()
295 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) in ffec_miigasket_setup()
301 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) in ffec_miigasket_setup()
210 RD2(struct ffec_softc *sc, bus_size_t off) RD2() function
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_sdhost.c | 251 RD2(struct bcm_sdhost_softc *sc, bus_size_t off) in RD2() function
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 13727 const RecordDecl *RD2) { in isLayoutCompatibleStruct() argument
13732 if (const CXXRecordDecl *D2CXX = dyn_cast<CXXRecordDecl>(RD2)) in isLayoutCompatibleStruct()
13733 RD2 = D2CXX->getStandardLayoutBaseWithFields(); in isLayoutCompatibleStruct()
13736 return llvm::equal(RD1->fields(), RD2->fields(), in isLayoutCompatibleStruct()
13745 const RecordDecl *RD2) { in isLayoutCompatibleUnion() argument
13747 for (auto *Field2 : RD2->fields()) in isLayoutCompatibleUnion()
13770 const RecordDecl *RD2) { in isLayoutCompatible() argument
13771 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
13775 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
13777 return isLayoutCompatibleStruct(C, RD1, RD2); in isLayoutCompatible()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3136 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3137 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
3145 .addReg(RD2) in emitMSACBranchPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4407 Register RD2 = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in emitVecCondBranchPseudo() local
4408 BuildMI(TrueBB, DL, TII->get(LoongArch::ADDI_W), RD2) in emitVecCondBranchPseudo()
4418 .addReg(RD2) in emitVecCondBranchPseudo()
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