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Searched refs:RD1 (Results 1 – 23 of 23) sorted by relevance

/freebsd/sys/dev/hdmi/
H A Ddwc_hdmi.c77 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & in dwc_hdmi_phy_wait_i2c_done()
84 val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) & in dwc_hdmi_phy_wait_i2c_done()
186 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_power()
197 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_enable_tmds()
208 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_pddq()
219 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_gen2_txpwron()
230 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_data_en_pol()
241 reg = RD1(sc, HDMI_PHY_CONF0); in dwc_hdmi_phy_sel_interface_control()
252 val = RD1(sc, HDMI_PHY_TST0); in dwc_hdmi_phy_test_clear()
268 val = RD1(sc, HDMI_FC_INVIDCONF); in dwc_hdmi_clear_overflow()
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H A Ddwc_hdmi.h46 RD1(struct dwc_hdmi_softc *sc, bus_size_t off) in RD1() function
/freebsd/sys/arm64/nvidia/tegra210/
H A Dmax77620.c257 rv = RD1(sc, MAX77620_REG_CID0 + i , buf + i); in max77620_get_version()
342 RD1(sc, MAX77620_REG_INTENLBT, &intenlbt); in max77620_intr()
343 RD1(sc, MAX77620_REG_INTLBT, &intlbt); in max77620_intr()
345 RD1(sc, MAX77620_REG_IRQTOP, &irqtop); in max77620_intr()
346 RD1(sc, MAX77620_REG_IRQTOPM, &irqtopm); in max77620_intr()
347 RD1(sc, MAX77620_REG_IRQSD, &irqsd); in max77620_intr()
348 RD1(sc, MAX77620_REG_IRQMASKSD, &irqmasksd); in max77620_intr()
349 RD1(sc, MAX77620_REG_IRQ_LVL2_L0_7, &irq_lvl2_l0_7); in max77620_intr()
350 RD1(sc, MAX77620_REG_IRQ_MSK_L0_7, &irq_msk_l0_7); in max77620_intr()
351 RD1(sc, MAX77620_REG_IRQ_LVL2_L8, &irq_lvl2_l8); in max77620_intr()
[all …]
H A Dmax77620_gpio.c211 rv = RD1(sc, pin->reg, &reg); in max77620_pinmux_config_node()
446 rv = RD1(sc, pin->reg, &reg); in max77620_gpio_get_mode()
527 rv = RD1(sc, pin->reg, &reg); in max77620_gpio_pin_setflags()
618 rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp); in max77620_gpio_pin_get()
643 rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp); in max77620_gpio_pin_toggle()
679 rv = RD1(sc, MAX77620_REG_PUE_GPIO, &sc->gpio_reg_pue); in max77620_gpio_attach()
685 rv = RD1(sc, MAX77620_REG_PDE_GPIO, &sc->gpio_reg_pde); in max77620_gpio_attach()
691 rv = RD1(sc, MAX77620_REG_AME_GPIO, &sc->gpio_reg_ame); in max77620_gpio_attach()
H A Dmax77620_regulators.c365 rv = RD1(sc->base_sc, sc->def->volt_reg, sel); in max77620_get_sel()
400 rv = RD1(sc->base_sc, sc->def->fps_reg, &val); in max77620_get_fps_src()
460 rv = RD1(sc->base_sc, sc->def->pwr_mode_reg, &val); in max77620_get_pwr_mode()
487 rv = RD1(sc->base_sc, sc->def->cfg_reg, &val); in max77620_get_pwr_ramp_delay()
557 RD1(sc->base_sc, sc->def->volt_reg, &val1); in max77620_regnode_init()
558 RD1(sc->base_sc, sc->def->cfg_reg, &val2); in max77620_regnode_init()
559 RD1(sc->base_sc, sc->def->fps_reg, &val3); in max77620_regnode_init()
H A Dmax77620.h224 #define RD1(sc, reg, val) max77620_read(sc, reg, val) macro
/freebsd/sys/arm/nvidia/
H A Das3722_gpio.c488 rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp); in as3722_gpio_pin_get()
490 rv = RD1(sc, AS3722_GPIO_SIGNAL_IN, &tmp); in as3722_gpio_pin_get()
513 rv = RD1(sc, AS3722_GPIO_SIGNAL_OUT, &tmp); in as3722_gpio_pin_toggle()
559 rv = RD1(sc, AS3722_GPIO0_CONTROL + i, &pin->pin_ctrl_reg); in as3722_gpio_attach()
H A Das3722.c197 rv = RD1(sc, AS3722_ASIC_ID1, &reg); in as3722_get_version()
206 rv = RD1(sc, AS3722_ASIC_ID2, &sc->chip_rev); in as3722_get_version()
H A Das3722_regulators.c389 rv = RD1(sc->base_sc, sc->def->volt_reg, sel); in as3722_read_sel()
418 rv = RD1(sc->base_sc, AS3722_FUSE7, &val); in as3722_sd0_is_low_voltage()
H A Das3722.h283 #define RD1(sc, reg, val) as3722_read(sc, reg, val) macro
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama5d3_gmac.dtsi43 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
53 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A GRXCK, conflicts with RD1 */
H A Dsama5d3.dtsi871 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
H A Dsama5d4.dtsi1332 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
/freebsd/sys/dev/tpm/
H A Dtpm_tis.c
/freebsd/sys/dev/iicbus/pmic/
H A Dact8846.h47 #define RD1(sc, reg, val) act8846_read(sc, reg, val) macro
H A Dact8846_regulator.c245 rv = RD1(sc->base_sc, sc->def->voltage_reg, sel); in act8846_read_sel()
/freebsd/sys/dev/sdhci/
H A Dsdhci.c81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) macro
237 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); in sdhci_dumpregs_buf()
239 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); in sdhci_dumpregs_buf()
241 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs_buf()
243 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); in sdhci_dumpregs_buf()
251 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); in sdhci_dumpregs_buf()
548 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) in sdhci_set_power()
552 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) in sdhci_set_power()
1286 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
1297 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
/freebsd/sys/dev/iicbus/controller/cadence/
H A Dcdnc_i2c.c113 #define RD1(sc, off) (bus_read_1((sc)->mem_res, (off))) macro
428 RD1(sc, CDNC_I2C_TRANS_SIZE) - 1); in cdnc_i2c_xfer_wr()
/freebsd/sys/arm/allwinner/
H A Daw_sid.c258 #define RD1(sc, reg) bus_read_1((sc)->res, (reg)) macro
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c262 RD1(struct bcm_sdhost_softc *sc, bus_size_t off) in RD1() function
827 val1 = RD1(sc, HC_POWER); in bcm_sdhost_read_1()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaChecking.cpp13726 static bool isLayoutCompatibleStruct(const ASTContext &C, const RecordDecl *RD1, in isLayoutCompatibleStruct() argument
13729 if (const CXXRecordDecl *D1CXX = dyn_cast<CXXRecordDecl>(RD1)) in isLayoutCompatibleStruct()
13730 RD1 = D1CXX->getStandardLayoutBaseWithFields(); in isLayoutCompatibleStruct()
13736 return llvm::equal(RD1->fields(), RD2->fields(), in isLayoutCompatibleStruct()
13744 static bool isLayoutCompatibleUnion(const ASTContext &C, const RecordDecl *RD1, in isLayoutCompatibleUnion() argument
13750 for (auto *Field1 : RD1->fields()) { in isLayoutCompatibleUnion()
13769 static bool isLayoutCompatible(const ASTContext &C, const RecordDecl *RD1, in isLayoutCompatible() argument
13771 if (RD1->isUnion() != RD2->isUnion()) in isLayoutCompatible()
13774 if (RD1->isUnion()) in isLayoutCompatible()
13775 return isLayoutCompatibleUnion(C, RD1, RD2); in isLayoutCompatible()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3130 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo() local
3131 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3143 .addReg(RD1) in emitMSACBranchPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4399 Register RD1 = MRI.createVirtualRegister(&LoongArch::GPRRegClass); in emitVecCondBranchPseudo() local
4400 BuildMI(FalseBB, DL, TII->get(LoongArch::ADDI_W), RD1) in emitVecCondBranchPseudo()
4416 .addReg(RD1) in emitVecCondBranchPseudo()