| /freebsd/crypto/openssl/ssl/quic/ |
| H A D | quic_rcidm.c | 134 } RCID; typedef
136 DEFINE_PRIORITY_QUEUE_OF(RCID);
137 DEFINE_LIST_OF(retiring, RCID);
194 PRIORITY_QUEUE_OF(RCID) * rcids;
203 RCID *cur_rcid;
246 static void rcidm_transition_rcid(QUIC_RCIDM *rcidm, RCID *rcid,
250 static void rcidm_check_rcid(QUIC_RCIDM *rcidm, RCID *rcid) in rcidm_check_rcid()
273 static int rcid_cmp(const RCID *a, const RCID *b) in rcid_cmp()
305 RCID *rcid, *rnext; in ossl_quic_rcidm_free()
342 static RCID *rcidm_create_rcid(QUIC_RCIDM *rcidm, uint64_t seq_num, in rcidm_create_rcid()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 231 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
232 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
398 const TargetRegisterClass *getRegClass(unsigned RCID) const;
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| H A D | AMDGPUTargetTransformInfo.h | 121 unsigned getNumberOfRegisters(unsigned RCID) const override;
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| H A D | SIInstrInfo.cpp | 5797 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass() argument
5803 switch (RCID) { in adjustAllocatableRegClass()
5805 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
5808 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
5811 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
5814 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
5817 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
5820 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
5827 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
5873 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
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| H A D | SIFoldOperands.cpp | 1048 int16_t RCID = Desc.operands()[UseOpIdx].RegClass; in tryFoldRegSeqSplat() local
1049 if (RCID == -1) in tryFoldRegSeqSplat()
1052 const TargetRegisterClass *OpRC = TRI->getRegClass(RCID); in tryFoldRegSeqSplat()
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| H A D | SIRegisterInfo.cpp | 3906 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
3907 switch ((int)RCID) { in getRegClass()
3915 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
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| H A D | AMDGPUTargetTransformInfo.cpp | 319 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
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| H A D | AMDGPUISelDAGToDAG.cpp | 373 unsigned RCID = N->getConstantOperandVal(0); in getOperandRegClass() local
375 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 719 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
720 if (RCID != -1) { in printRegularOperand()
721 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
794 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
795 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 997 unsigned RCID; in getRegClassConstraint() local
999 F.hasRegClassConstraint(RCID)) in getRegClassConstraint()
1000 return TRI->getRegClass(RCID); in getRegClassConstraint()
1947 unsigned RCID; in print() local
1948 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in print()
1950 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1952 OS << ":RC" << RCID; in print()
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| H A D | TargetInstrInfo.cpp | 2076 unsigned RCID; in createMIROperandComment() local
2077 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in createMIROperandComment()
2079 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
2081 OS << ":RC" << RCID; in createMIROperandComment()
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| /freebsd/crypto/openssl/doc/designs/quic-design/ |
| H A D | glossary.md | 94 connection if found in the DCID field of an incoming packet. See also RCID.
228 **RCID:** Remote CID. Refers to a CID which has been provided to us by a peer
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 278 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline() argument
279 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline()
282 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
283 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods()
346 bool isVRegWithInputMods(unsigned RCID) const { return isRegClass(RCID); } in isVRegWithInputMods()
448 bool isRegClass(unsigned RCID) const;
452 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
453 return isRegOrInline(RCID, type) && !hasModifiers(); in isRegOrInlineNoMods()
2221 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
2222 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 2650 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
2651 switch (RCID) { in getRegBitWidth()
2800 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
2801 return getRegBitWidth(RCID) / 8; in getRegOperandSize()
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| H A D | AMDGPUBaseInfo.h | 1576 unsigned getRegBitWidth(unsigned RCID);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1613 unsigned RCID; in handleSpecialFP() local
1632 if (F.hasRegClassConstraint(RCID)) { in handleSpecialFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 234 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
236 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
2683 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
2685 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
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