| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 203 bool isSGPRClassID(unsigned RCID) const {
204 return isSGPRClass(getRegClass(RCID)); in isVGPRClass()
363 const TargetRegisterClass *getRegClass(unsigned RCID) const;
197 isSGPRClassID(unsigned RCID) isSGPRClassID() argument
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| H A D | AMDGPUTargetTransformInfo.h | 120 unsigned getNumberOfRegisters(unsigned RCID) const;
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| H A D | SIInstrInfo.cpp | 5550 const MCInstrDesc &TID, unsigned RCID, in adjustAllocatableRegClass() argument
5556 switch (RCID) { in adjustAllocatableRegClass()
5558 RCID = AMDGPU::VGPR_32RegClassID; in adjustAllocatableRegClass()
5561 RCID = AMDGPU::VReg_64RegClassID; in adjustAllocatableRegClass()
5564 RCID = AMDGPU::VReg_96RegClassID; in adjustAllocatableRegClass()
5567 RCID = AMDGPU::VReg_128RegClassID; in adjustAllocatableRegClass()
5570 RCID = AMDGPU::VReg_160RegClassID; in adjustAllocatableRegClass()
5573 RCID = AMDGPU::VReg_512RegClassID; in adjustAllocatableRegClass()
5580 return RI.getProperlyAlignedRC(RI.getRegClass(RCID)); in adjustAllocatableRegClass()
5626 unsigned RCID = Desc.operands()[OpNo].RegClass; in getOpRegClass() local
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| H A D | SIRegisterInfo.cpp | 3141 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
3142 switch ((int)RCID) { in getRegClass()
3151 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
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| H A D | AMDGPUTargetTransformInfo.cpp | 309 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
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| H A D | AMDGPUISelDAGToDAG.cpp | 378 unsigned RCID = N->getConstantOperandVal(0); in getOperandRegClass() local
380 Subtarget->getRegisterInfo()->getRegClass(RCID); in getOperandRegClass()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstr.cpp | 970 unsigned RCID; in getRegClassConstraint() local
972 F.hasRegClassConstraint(RCID)) in getRegClassConstraint()
973 return TRI->getRegClass(RCID); in getRegClassConstraint()
1836 unsigned RCID; in print() local
1837 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in print()
1839 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1841 OS << ":RC" << RCID; in print()
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| H A D | TargetInstrInfo.cpp | 1766 unsigned RCID; in createMIROperandComment() local
1767 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) { in createMIROperandComment()
1769 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1771 OS << ":RC" << RCID; in createMIROperandComment()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUInstPrinter.cpp | 809 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
810 if (RCID != -1) { in printRegularOperand()
811 const MCRegisterClass RC = MRI.getRegClass(RCID); in printRegularOperand()
895 int RCID = Desc.operands()[OpNo].RegClass; in printRegularOperand() local
896 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printRegularOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.cpp | 2401 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
2402 switch (RCID) { in getRegBitWidth()
2547 unsigned RCID = Desc.operands()[OpNo].RegClass; in getRegOperandSize() local
2548 return getRegBitWidth(RCID) / 8; in getRegOperandSize()
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| H A D | AMDGPUBaseInfo.h | 1345 unsigned getRegBitWidth(unsigned RCID);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 270 bool isRegOrInline(unsigned RCID, MVT type) const { in isRegOrInline() argument
271 return isRegClass(RCID) || isInlinableImm(type); in isRegOrInline()
274 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
275 return isRegOrInline(RCID, type) || isLiteralImm(type); in isRegOrImmWithInputMods()
410 bool isRegClass(unsigned RCID) const;
414 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
415 return isRegOrInline(RCID, type) && !hasModifiers(); in isRegOrInlineNoMods()
2144 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
2145 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2826 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 1596 unsigned RCID; in handleSpecialFP() local
1615 if (F.hasRegClassConstraint(RCID)) { in handleSpecialFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 216 unsigned RCID = getRegClassIDForVecVT(ContainerVT); in RISCVTargetLowering() local
218 addRegisterClass(VT, TRI.getRegClass(RCID)); in RISCVTargetLowering()
2543 for (const unsigned RCID : in decomposeSubvectorInsertExtractToSubRegs()
2545 if (VecRegClassID > RCID && SubRegClassID <= RCID) { in decomposeSubvectorInsertExtractToSubRegs()
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