270   bool isRegOrInline(unsigned RCID, MVT type) const {  in isRegOrInline()  argument
271     return isRegClass(RCID) || isInlinableImm(type);  in isRegOrInline()
274   bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {  in isRegOrImmWithInputMods()  argument
275     return isRegOrInline(RCID, type) || isLiteralImm(type);  in isRegOrImmWithInputMods()
410   bool isRegClass(unsigned RCID) const;
414   bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {  in isRegOrInlineNoMods()  argument
415     return isRegOrInline(RCID, type) && !hasModifiers();  in isRegOrInlineNoMods()
2144 bool AMDGPUOperand::isRegClass(unsigned RCID) const {  in isRegClass()
2145   return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());  in isRegClass()
2826   int RCID = getRegClass(RegKind, RegWidth);  in getRegularReg()  local
2827   if (RCID == -1) {  in getRegularReg()
2833   const MCRegisterClass RC = TRI->getRegClass(RCID);  in getRegularReg()