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Searched refs:RB (Results 1 – 25 of 68) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td19 bits<5> RB;
25 let Inst{16-20} = RB;
32 let RB = 0;
46 bits<5> RB;
51 let Inst{16-20} = RB;
60 bits<5> RB;
66 let Inst{16-20} = RB;
73 let RB = 0;
87 bits<5> RB;
94 let Inst{16-20} = RB;
[all …]
H A DPPCInstrDFP.td19 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
20 "dadd", "$RST, $RA, $RB", IIC_FPGeneral, []>;
22 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
23 "daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
26 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
27 "dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>;
29 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
30 "dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
33 defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
34 "dmul", "$RST, $RA, $RB", IIC_FPGeneral, []>;
[all …]
H A DPPCInstrFuture.td19 bits<5> RB;
28 let Inst{16-20} = RB;
50 (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
51 "subfus", "$RT, $L, $RA, $RB", []>;
56 def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
57 "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
59 def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
60 "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
63 (ins memr:$RA, g8rc:$RB),
64 "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
[all …]
H A DPPCInstr64Bit.td335 def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
339 def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
344 def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
350 def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
355 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB),
356 "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64,
361 def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
365 def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr),
426 def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB),
427 "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64,
[all …]
H A DPPCInstrHTM.td41 let RB = 0;
45 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
46 "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
50 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
51 "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
55 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
56 "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
60 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
61 "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
73 let RB = 0;
[all …]
H A DPPCInstrInfo.td1708 def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr",
1711 def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr",
1714 def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr",
1717 def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr",
1720 def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr",
1724 def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr),
1729 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
1732 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
1737 def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
1739 def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr),
[all …]
H A DPPCInstrFormats.td448 bits<5> RB;
456 let Inst{16-20} = RB;
491 bits<5> RB;
497 let Inst{16-20} = RB;
521 let RB = 0;
563 let RB = 0;
573 bits<5> RB;
579 let Inst{16-20} = RB;
589 bits<5> RB;
594 let Inst{16-20} = RB;
[all …]
H A DPPCInstrAltivec.td269 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
270 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
271 [(set Ty:$RT, (IntID Ty:$RA, Ty:$RB, Ty:$RC))]>;
277 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
278 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
279 [(set OutTy:$RT, (IntID InTy:$RA, InTy:$RB, InTy:$RC))]>;
285 : VAForm_1a<xo, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC),
286 !strconcat(opc, " $RT, $RA, $RB, $RC"), IIC_VecFP,
288 (IntID In1Ty:$RA, In1Ty:$RB, In2Ty:$RC))]>;
346 let RB = 0;
[all …]
H A DPPCExpandAtomicPseudoInsts.cpp153 Register RB = MI.getOperand(3).getReg(); in expandAtomicRMW128() local
159 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
201 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicRMW128()
229 Register RB = MI.getOperand(3).getReg(); in expandAtomicCmpSwap128() local
257 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
277 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB); in expandAtomicCmpSwap128()
H A DPPCInstrP10.td388 // VX-Form: [PO VRT RA RB XO].
584 let RB = 0;
879 bits<5> RB;
885 let Inst{16-20} = RB;
1163 def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr),
1172 def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr),
1638 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
1639 "vextdubvlx $RT, $RA, $RB, $RC",
1643 v16i8:$RB,
1646 (ins vrrc:$RA, vrrc:$RB, gprc:$RC),
[all …]
/freebsd/contrib/llvm-project/clang/lib/Rewrite/
H A DHTMLRewrite.cpp59 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E, in HighlightRange() argument
63 RB.InsertTextAfter(B, StartTag); in HighlightRange()
64 RB.InsertTextBefore(E, EndTag); in HighlightRange()
78 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag); in HighlightRange()
97 RB.InsertTextAfter(i, StartTag); in HighlightRange()
143 RewriteBuffer &RB = R.getEditBuffer(FID); in EscapeText() local
156 RB.ReplaceText(FilePos, 1, "&nbsp;"); in EscapeText()
160 RB.ReplaceText(FilePos, 1, "<hr>"); in EscapeText()
169 RB.ReplaceText(FilePos, 1, in EscapeText()
173 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces)); in EscapeText()
[all …]
H A DRewriter.cpp63 const RewriteBuffer &RB = I->second; in getRangeSize() local
64 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange); in getRangeSize()
65 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange); in getRangeSize()
114 const RewriteBuffer &RB = I->second; in getRewrittenText() local
115 EndOff = RB.getMappedOffset(EndOff, true); in getRewrittenText()
116 StartOff = RB.getMappedOffset(StartOff); in getRewrittenText()
124 RewriteBuffer::iterator Start = RB.begin(); in getRewrittenText()
300 RewriteBuffer &RB = getEditBuffer(FID); in IncreaseIndentation() local
308 RB.InsertText(offs, indent, /*InsertAfter=*/false); in IncreaseIndentation()
/freebsd/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
H A Dcombined.h193 AllocationRingBuffer *RB = getRingBuffer(); in enableRingBuffer() local
194 if (RB) in enableRingBuffer()
195 RB->Depot->enable(); in enableRingBuffer()
201 AllocationRingBuffer *RB = getRingBuffer(); in disableRingBuffer() local
202 if (RB) in disableRingBuffer()
203 RB->Depot->disable(); in disableRingBuffer()
854 AllocationRingBuffer *RB = getRingBuffer(); in getStackDepotAddress() local
855 return RB ? reinterpret_cast<char *>(RB->Depot) : nullptr; in getStackDepotAddress()
860 AllocationRingBuffer *RB = getRingBuffer(); in getStackDepotSize() local
861 return RB ? RB->StackDepotSize : 0; in getStackDepotSize()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankSelect.cpp130 const RegisterBank *RB) { in reAssignRegBankOnDef() argument
137 Register NewReg = MRI.createVirtualRegister({RB, Ty}); in reAssignRegBankOnDef()
169 const RegisterBank *RB) { in constrainRegBankUse() argument
173 Register NewReg = MRI.createVirtualRegister({RB, Ty}); in constrainRegBankUse()
262 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg); in runOnMachineFunction() local
264 RBSHelper.reAssignRegBankOnDef(MI, DefOP, RB); in runOnMachineFunction()
267 MRI.setRegBank(DefReg, *RB); in runOnMachineFunction()
284 const RegisterBank *RB = RBSHelper.getRegBankToAssign(UseReg); in runOnMachineFunction() local
285 RBSHelper.constrainRegBankUse(MI, UseOP, RB); in runOnMachineFunction()
H A DAMDGPURegBankLegalizeHelper.cpp413 const RegisterBank *RB = MRI.getRegBank(MI.getOperand(0).getReg()); in lower() local
417 Hi = B.buildConstant({RB, S32}, 0); in lower()
422 auto ShiftAmt = B.buildConstant({RB, S32}, 31); in lower()
423 Hi = B.buildAShr({RB, S32}, MI.getOperand(1).getReg(), ShiftAmt); in lower()
427 Hi = B.buildUndef({RB, S32}); in lower()
726 [[maybe_unused]] const RegisterBank *RB = MRI.getRegBank(Reg); in applyMappingDst() local
755 assert(RB == getRegBankFromID(MethodIDs[OpIdx])); in applyMappingDst()
778 assert(RB == getRegBankFromID(MethodIDs[OpIdx])); in applyMappingDst()
784 assert(RB == SgprRB); in applyMappingDst()
796 assert(RB == SgprRB); in applyMappingDst()
[all …]
H A DAMDGPURegBankLegalize.cpp119 const RegisterBank *RB = MRI.getRegBankOrNull(Reg); in isLaneMask() local
120 if (RB && RB->getID() == AMDGPU::VCCRegBankID) in isLaneMask()
247 const RegisterBank *RB = MRI.getRegBankOrNull(Reg); in getAnySgprS1() local
248 if (RB && RB->getID() == AMDGPU::SGPRRegBankID) { in getAnySgprS1()
H A DAMDGPURegBankCombiner.cpp381 auto &RB = *MRI.getRegBank(AmtReg); in applyCanonicalizeZextShiftAmt() local
389 MRI.setRegBank(NewExt.getReg(0), RB); in applyCanonicalizeZextShiftAmt()
390 MRI.setRegBank(Mask.getReg(0), RB); in applyCanonicalizeZextShiftAmt()
391 MRI.setRegBank(And.getReg(0), RB); in applyCanonicalizeZextShiftAmt()
/freebsd/contrib/llvm-project/clang/lib/Frontend/Rewrite/
H A DRewriteMacros.cpp93 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); in RewriteMacrosInInput() local
132 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
138 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); in RewriteMacrosInInput()
168 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); in RewriteMacrosInInput()
186 RB.InsertTextBefore(EndPos, "*/"); in RewriteMacrosInInput()
202 RB.InsertTextBefore(InsertPos, Expansion); in RewriteMacrosInInput()
/freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_ring_buffer.h27 RingBuffer *RB = reinterpret_cast<RingBuffer*>(Ptr); in New() local
29 RB->last_ = RB->next_ = reinterpret_cast<T*>(End - sizeof(T)); in New()
30 return RB; in New()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp74 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
77 unsigned getPtrLoadStoreOp(const LLT &Ty, const RegisterBank &RB,
134 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
176 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
177 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
187 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
202 if (RB.getID() == X86::PSRRegBankID) { in getRegClass()
266 const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank); in selectDebugInstr() local
267 RC = getRegClass(Ty, RB); in selectDebugInstr()
454 const RegisterBank &RB, in getPtrLoadStoreOp() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp254 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints() local
255 if (RB == &PPC::FPRRegBank) in hasFPConstraints()
257 if (RB == &PPC::GPRRegBank) in hasFPConstraints()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp361 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { in addNodeIDRegType()
362 ID.AddPointer(RB); in addNodeIDRegType()
372 if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB)) in addNodeIDRegType() local
373 addNodeIDRegType(RB); in addNodeIDRegType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterBankInfo.cpp94 if (auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank)) in getRegBank() local
95 return RB; in getRegBank()
139 const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank); in constrainGenericRegister() local
141 if (RB && !RB->covers(RC)) in constrainGenericRegister()
/freebsd/sys/contrib/openzfs/module/lua/
H A Dlvm.c552 #define RB(i) check_exp(getBMode(GET_OPCODE(i)) == OpArgR, base+GETARG_B(i)) macro
619 setobjs2s(L, ra, RB(i)); in luaV_execute()
650 Protect(luaV_gettable(L, RB(i), RKC(i), ra)); in luaV_execute()
674 StkId rb = RB(i); in luaV_execute()
700 TValue *rb = RB(i); in luaV_execute()
710 TValue *rb = RB(i); in luaV_execute()
715 Protect(luaV_objlen(L, ra, RB(i))); in luaV_execute()
765 TValue *rb = RB(i); in luaV_execute()

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