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Searched refs:RA (Results 1 – 25 of 154) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td18 bits<5> RA;
24 let Inst{11-15} = RA;
38 let RA = 0;
45 bits<5> RA;
50 let Inst{11-15} = RA;
59 bits<5> RA;
65 let Inst{11-15} = RA;
79 let RA = 0;
86 bits<5> RA;
93 let Inst{11-15} = RA;
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H A DPPCInstr64Bit.td218 (ins (memrix $D, $RA):$src),
228 (ins (memrix $D, $RA):$src),
335 def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
339 def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
344 def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr),
350 def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr),
355 def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB),
356 "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64,
361 def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
365 def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr),
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H A DPPCInstrFuture.td18 bits<5> RA;
27 let Inst{11-15} = RA;
50 (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
51 "subfus", "$RT, $L, $RA, $RB", []>;
56 def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
57 "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
59 def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
60 "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
63 (ins memr:$RA, g8rc:$RB),
64 "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
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H A DPPCInstrDFP.td19 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
20 "dadd", "$RST, $RA, $RB", IIC_FPGeneral, []>;
22 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
23 "daddq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
26 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
27 "dsub", "$RST, $RA, $RB", IIC_FPGeneral, []>;
29 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
30 "dsubq", "$RST, $RA, $RB", IIC_FPGeneral, []>;
33 defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
34 "dmul", "$RST, $RA, $RB", IIC_FPGeneral, []>;
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H A DPPCInstrHTM.td38 (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR,
45 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
46 "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
50 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
51 "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
55 (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB),
56 "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>,
60 (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB),
61 "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>,
69 (outs), (ins gprc:$RA), "treclaim. $RA",
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H A DPPCMacroFusion.cpp105 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints() local
106 if (!RA.isReg()) in checkOpConstraints()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
205 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
209 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
216 const MachineOperand &RA in checkOpConstraints() local
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H A DPPCInstrP10.td28 // * [FR|R|V|X|B][A-Z] - register source (i.e. FRA, RA, XB, etc.)
188 bits<5> RA;
202 let Inst{43-47} = RA;
210 bits<5> RA;
224 let Inst{43-47} = RA;
262 bits<5> RA;
275 let Inst{43-47} = RA;
280 // PO TX T RA d1 ]
286 bits<5> RA;
302 let Inst{43-47} = RA;
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H A DPPCInstrInfo.td1586 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1595 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB,
1682 def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr",
1685 def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr",
1688 def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr",
1691 def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr",
1694 def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr",
1698 def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr),
1703 def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
1706 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr),
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H A DPPCInstrFormats.td241 bits<5> RA;
247 let Inst{11-15} = RA;
281 bits<5> RA;
288 let Inst{11-15} = RA;
296 let RA = 0;
305 let RA = R;
314 bits<5> RA;
325 let Inst{43-47} = RA;
336 let RA = 0;
345 bits<5> RA;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFDeadCode.cpp89 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) { in scanInstr()
90 if (!LiveNodes.count(RA.Id)) in scanInstr()
91 WorkQ.push_back(RA.Id); in scanInstr()
136 auto RA = DFG.addr<RefNode*>(N); in collect() local
137 if (DFG.IsDef(RA)) in collect()
138 processDef(RA, WorkQ); in collect()
140 processUse(RA, WorkQ); in collect()
146 auto RA = DFG.addr<RefNode*>(N); in collect() local
147 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n"; in collect()
160 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) in collect()
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H A DHexagonRDFOpt.cpp171 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) { in run()
172 R2I.insert(std::make_pair(RA.Id, SA.Id)); in run()
173 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id)) in run()
206 for (NodeAddr<RefNode*> RA : Refs) in removeOperand()
207 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); in removeOperand()
211 for (NodeAddr<RefNode*> RA : Refs) { in removeOperand()
212 unsigned N = OpMap[RA.Id]; in removeOperand()
214 RA.Addr->setRegRef(&MI->getOperand(N), DFG); in removeOperand()
216 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG); in removeOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocPriorityAdvisor.cpp58 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
60 MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI()); in getAdvisor()
105 const RAGreedy &RA, in RegAllocPriorityAdvisor() argument
107 : RA(RA), LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()), in RegAllocPriorityAdvisor()
109 RegClassInfo(RA.getRegClassInfo()), Indexes(Indexes), in RegAllocPriorityAdvisor()
111 RA.getRegClassPriorityTrumpsGlobalness()), in RegAllocPriorityAdvisor()
112 ReverseLocalAssignment(RA.getReverseLocalAssignment()) {} in RegAllocPriorityAdvisor()
H A DRegAllocEvictionAdvisor.cpp81 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
82 return std::make_unique<DefaultEvictionAdvisor>(MF, RA); in getAdvisor()
127 const RAGreedy &RA) in RegAllocEvictionAdvisor() argument
128 : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()), in RegAllocEvictionAdvisor()
129 LIS(RA.getLiveIntervals()), VRM(RA.getVirtRegMap()), in RegAllocEvictionAdvisor()
131 RegClassInfo(RA.getRegClassInfo()), RegCosts(TRI->getRegisterCosts(MF)), in RegAllocEvictionAdvisor()
152 bool CanSplit = RA.getExtraInfo().getStage(B) < RS_Spill; in shouldEvict()
202 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost()
224 if (RA.getExtraInfo().getStage(*Intf) == RS_Done) in canEvictInterferenceBasedOnCost()
239 unsigned IntfCascade = RA.getExtraInfo().getCascade(Intf->reg()); in canEvictInterferenceBasedOnCost()
H A DRDFGraph.cpp111 static void printRefHeader(raw_ostream &OS, const Ref RA, in printRefHeader() argument
113 OS << Print(RA.Id, G) << '<' << Print(RA.Addr->getRegRef(G), G) << '>'; in printRefHeader()
114 if (RA.Addr->getFlags() & NodeAttrs::Fixed) in printRefHeader()
789 Ref RA = NA; in cloneNode() local
790 RA.Addr->setReachingDef(0); in cloneNode()
791 RA.Addr->setSibling(0); in cloneNode()
1136 NodeList DataFlowGraph::getRelatedRefs(Instr IA, Ref RA) const { in getRelatedRefs()
1137 assert(IA.Id != 0 && RA.Id != 0); in getRelatedRefs()
1140 NodeId Start = RA.Id; in getRelatedRefs()
1142 Refs.push_back(RA); in getRelatedRefs()
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H A DMLRegallocPriorityAdvisor.cpp
H A DMLRegAllocPriorityAdvisor.cpp94 MLPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA,
142 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
154 MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI(), Runner.get()); in getAdvisor()
179 DevelopmentModePriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA, in DevelopmentModePriorityAdvisor() argument
182 : MLPriorityAdvisor(MF, RA, Indexes, Runner), Log(Log) {} in DevelopmentModePriorityAdvisor()
261 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override { in getAdvisor() argument
269 MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI(), Runner.get(), in getAdvisor()
288 const RAGreedy &RA, in MLPriorityAdvisor() argument
291 : RegAllocPriorityAdvisor(MF, RA, Indexes), DefaultAdvisor(MF, RA, Indexes), in MLPriorityAdvisor()
299 LiveRangeStage Stage = RA.getExtraInfo().getStage(LI); in getPriorityImpl()
H A DRegAllocPriorityAdvisor.h34 RegAllocPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA,
38 const RAGreedy &RA;
51 DefaultPriorityAdvisor(const MachineFunction &MF, const RAGreedy &RA, in DefaultPriorityAdvisor() argument
53 : RegAllocPriorityAdvisor(MF, RA, Indexes) {} in DefaultPriorityAdvisor()
69 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
H A DRegAllocEvictionAdvisor.h122 RegAllocEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA);
138 const RAGreedy &RA; variable
177 getAdvisor(const MachineFunction &MF, const RAGreedy &RA) = 0;
206 DefaultEvictionAdvisor(const MachineFunction &MF, const RAGreedy &RA) in DefaultEvictionAdvisor() argument
207 : RegAllocEvictionAdvisor(MF, RA) {} in DefaultEvictionAdvisor()
H A DMLRegallocEvictAdvisor.cpp
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt3 The Ring Accelerator (RA) is a machine which converts read/write accesses
5 circular data structure in memory. The RA eliminates the need for each DMA
9 source interface on the RA) and the RA replaces the address for the transaction
14 management of the packet queues. The K3 SoCs can have more than one RA instances
21 "rt" - The RA Ring Real-time Control/Status Registers
22 "fifos" - The RA Queues Registers
23 "proxy_gcfg" - The RA Proxy Global Config Registers
24 "proxy_target" - The RA Proxy Datapath Registers
25 - ti,num-rings : Number of rings supported by RA
/freebsd/contrib/lua/src/
H A Dlvm.c905 StkId ra = RA(i); \
934 StkId ra = RA(i); \
944 StkId ra = RA(i); \
954 StkId ra = RA(i); \
984 StkId ra = RA(i); \
998 StkId ra = RA(i); \
1013 StkId ra = RA(i); \
1033 StkId ra = RA(i); \
1063 #define RA(i) (base+GETARG_A(i)) macro
1080 { if (l_unlikely(trap)) { updatebase(ci); ra = RA(i); } }
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/freebsd/crypto/openssl/crypto/bn/asm/
H A Dbn-c64xplus.asm38 .asg B3,RA
54 [!B0] BNOP RA
76 BNOP RA,4
84 [!B0] BNOP RA
102 BNOP RA,4
110 [!B0] BNOP RA
125 SPKERNEL 2,0 ; fully overlap BNOP RA,5
128 BNOP RA,5
135 [!B0] BNOP RA
149 SPKERNEL 0,0 ; fully overlap BNOP RA,5
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/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DRelocationResolver.cpp468 int64_t RA = Addend; in resolveRISCV()
474 return (S + RA) & 0xFFFFFFFF; in resolveRISCV()
476 return (S + RA - Offset) & 0xFFFFFFFF; in resolveRISCV()
478 return S + RA; in resolveRISCV()
480 return (A & 0xC0) | ((S + RA) & 0x3F); in resolveRISCV()
482 return (A & 0xC0) | (((A & 0x3F) - (S + RA)) & 0x3F); in resolveRISCV()
484 return (S + RA) & 0xFF; in resolveRISCV()
486 return (A + (S + RA)) & 0xFF; in resolveRISCV()
488 return (A - (S + RA)) & 0xFF; in resolveRISCV()
490 return (S + RA) in resolveRISCV()
469 int64_t RA = Addend; resolveRISCV() local
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/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DDeadArgumentElimination.h130 bool isLive(const RetOrArg &RA);
131 void markValue(const RetOrArg &RA, Liveness L,
133 void markLive(const RetOrArg &RA);
135 void propagateLiveness(const RetOrArg &RA);
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DDeadArgumentElimination.cpp660 void DeadArgumentEliminationPass::markValue(const RetOrArg &RA, Liveness L, in markValue() argument
664 markLive(RA); in markValue()
667 assert(!isLive(RA) && "Use is already live!"); in markValue()
671 markLive(RA); in markValue()
676 Uses.emplace(MaybeLiveUse, RA); in markValue()
700 void DeadArgumentEliminationPass::markLive(const RetOrArg &RA) { in markLive() argument
701 if (isLive(RA)) in markLive()
704 LiveValues.insert(RA); in markLive()
707 << RA.getDescription() << " live\n"); in markLive()
708 propagateLiveness(RA); in markLive()
[all …]

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