Home
last modified time | relevance | path

Searched refs:R9 (Results 1 – 25 of 86) sorted by relevance

1234

/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td64 def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>, DwarfRegNum<[9]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td34 def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp218 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
223 XCore::R8, XCore::R9, in getCalleeSavedRegs()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S68 #define c63 R9
76 #define maxneg R9
203 #define c63 R9
211 #define maxneg R9
338 #define maxneg R9
H A Dfastmath2_ldlib_asm.S60 #define c63 R9
159 #define c63 R9
252 #define mantxl_ R9
265 #define kp R9
H A Dfastmath2_dlib_asm.S66 #define c63 R9
167 #define c63 R9
270 #define kb R9
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
270 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
275 def CSR_Win_AAPCS_CFGuard_Check : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7,
289 R11, R10, R9, R8,
292 def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
310 R10, R9, R8,
317 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
321 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
323 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
332 (sub CSR_AAPCS_ThisReturn, R9))>;
[all …]
H A DARMBaseRegisterInfo.h54 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
66 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
81 case R8: case R9: case R10: case R12: in isSplitFPArea1Register()
H A DARMTargetObjectFile.cpp58 MCRegister ARMElfTargetObjectFile::getStaticBase() const { return ARM::R9; } in getStaticBase()
H A DARMSLSHardening.cpp143 {"__llvm_slsblr_thunk_arm_r9", ARM::R9, false},
157 {"__llvm_slsblr_thunk_thumb_r9", ARM::R9, true},
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp74 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
99 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
150 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
H A DPPCCallingConv.td78 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
89 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
223 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
238 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Derfc_1u8.c36 #define R9 -0x1.4f2094f2094f2p-3 macro
111 double p10 = fma (Q9 * r, p9, p8) * R9; in erfc()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td45 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
91 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
106 def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>;
122 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFFrameLowering.cpp38 SavedRegs.reset(BPF::R9); in determineCalleeSaves()
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
/freebsd/crypto/openssl/test/certs/
H A Dbadcn1-key.pem2 MIIEvwIBADANBgkqhkiG9w0BAQEFAASCBKkwggSlAgEAAoIBAQDN9WI6OyxnW+R9
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h225 UINT64 R9; member
296 UINT64 R9; member
500 UINT32 R9; member
765 UINT64 R9; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h64 case Lanai::R9: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
567 // not split across register and stack. As such, do not allow using R9
571 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [R9]>>>,
573 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
680 [RCX , RDX , R8 , R9 ]>>,
693 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
696 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
718 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
[all …]
H A DX86CallingConv.cpp87 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9}; in CC_X86_64_VectorCallGetGPRs()
145 // If R9 was already assigned it means that we are after the fourth element in CC_X86_64_VectorCall()
148 if (State.isAllocated(X86::R9)) { in CC_X86_64_VectorCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td46 CCIfType<[i32], CCAssignToReg<[RV, R9]>>
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwm8960.txt32 gpio-cfg[0]: ALRCGPIO of R9 (Audio interface)

1234