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Searched refs:R6 (Results 1 – 25 of 75) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp39 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
44 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
49 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
55 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td61 def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>, DwarfRegNum<[6]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
48 R4, R5, R6, R7, R8, R9, R10,
55 R4, R5, R6, R7, R8, R9, R10,
H A DXCoreRegisterInfo.cpp212 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
217 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath_dlib_asm.S66 #define expd R6
73 #define zerol R6
201 #define expd R6
208 #define zerol R6
335 #define zero0l R6
H A Dfastmath2_dlib_asm.S64 #define expd R6
165 #define expd R6
377 #define mask R6
H A Dfastmath2_ldlib_asm.S58 #define expd R6
157 #define expd R6
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td122 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
275 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
284 def CSR_ATPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
288 def CSR_Win_SplitFP : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
298 R6, R5, R4, (sequence "D%u", 15, 0))>;
319 def CSR_AAPCS_SplitPush_R11 : CalleeSavedRegs<(add R10, R9, R8, R7, R6, R5, R4,
323 R7, R6, R5, R4,
331 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
337 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
345 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
H A DARMSLSHardening.cpp140 {"__llvm_slsblr_thunk_arm_r6", ARM::R6, false},
154 {"__llvm_slsblr_thunk_thumb_r6", ARM::R6, true},
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp72 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
150 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
H A DPPCCallingConv.td76 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
87 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
221 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
236 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td24 CCAssignToReg<[R6, R7, R18, R19]>>>>,
36 CCIfNotVarArg<CCIfType<[i32], CCAssignToReg<[ R6, R7, R18, R19 ]>>>,
H A DLanaiRegisterInfo.td48 R6, R7, R18, R19, // registers for passing arguments
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFCallingConv.td48 def CSR : CalleeSavedRegs<(add R6, R7, R8, R9, R10)>;
49 def CSR_PreserveAll : CalleeSavedRegs<(add R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10)>;
H A DBPFFrameLowering.cpp34 SavedRegs.reset(BPF::R6); in determineCalleeSaves()
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Derfc_1u8.c33 #define R6 -0x1.b6db6db6db6dbp-3 macro
108 double p7 = fma (Q6 * r, p6, p5) * R6; in erfc()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h115 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4) macro
116 R6(0), R6(2), R6(1), R6(3)
119 #undef R6
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td42 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
92 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
121 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1)>;
125 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp99 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
215 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h293 UINT64 R6; member
463 UINT64 R6; member
497 UINT32 R6; member
762 UINT64 R6; member
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h57 case Lanai::R6: in getLanaiRegisterNumbering()
/freebsd/secure/caroot/trusted/
H A DGlobalSign_Root_CA_-_R6.pem2 ## GlobalSign Root CA - R6
17 Issuer: OU=GlobalSign Root CA - R6, O=GlobalSign, CN=GlobalSign
21 Subject: OU=GlobalSign Root CA - R6, O=GlobalSign, CN=GlobalSign
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCCallingConv.td32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td44 // care about the ABI. (R6 is an argument register too, but is
69 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, R8, SpLim
113 // The first 5 integer arguments are passed in R2-R6. Note that R6
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dwm8903.txt20 - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the

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