Home
last modified time | relevance | path

Searched refs:R15 (Results 1 – 25 of 62) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td37 def RCA : LanaiReg<15, "rca", [R15]>, DwarfRegAlias<R15>;
49 R15, RCA, // register for constant addresses
H A DLanaiRegisterInfo.cpp58 Reserved.set(Lanai::R15); in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
H A DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td70 def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>, DwarfRegNum<[15]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td51 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
88 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
103 def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
157 // Lower 16-bit pair registers in R0..R15, only used in inline assembly.
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td67 def R15 : CSKYReg<15, "r15", ["lr"]>, DwarfRegNum<[15]>;
154 (sequence "R%u", 18, 25), R15, (sequence "R%u", 4, 11),
160 // Register class for R0 - R15.
161 // Some 16-bit integer instructions can only access R0 - R15.
163 (add (sequence "R%u", 0, 3), (sequence "R%u", 12, 13), R15,
H A DCSKYCallingConv.td13 def CSR_I32 : CalleeSavedRegs<(add R8, R15, (sequence "R%u", 4, 7),
21 def CSR_GPR_ISR : CalleeSavedRegs<(add R8, R15,
H A DCSKYRegisterInfo.cpp27 : CSKYGenRegisterInfo(CSKY::R15, 0, 0, 0) {} in CSKYRegisterInfo()
64 markSuperRegs(Reserved, CSKY::R15); // lr in getReservedRegs()
H A DCSKYFrameLowering.cpp451 SavedRegs.set(CSKY::R15); in determineCalleeSaves()
453 CFI->setLRIsSpilled(SavedRegs.test(CSKY::R15)); in determineCalleeSaves()
H A DCSKYInstrFormats.td63 let Defs = [ R15 ];
165 let Uses = [ R15 ];
248 // Format< OP[6] | SOP[5] | PCODE[5] | 0000[4] | 000 | R28 | LIST2[3] | R15 |
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td194 // 2) R14, R15 and R28 are reserved for PLT handling and therefore are
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
417 let Defs = [R14, R15, R28] in
420 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
423 let Defs = [R14, R15, R28, P0] in
426 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S254 #define mantxh R15
255 #define mantx R15:14
H A Dfastmath2_dlib_asm.S274 #define min R15:14
275 #define minh R15
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h78 case Lanai::R15: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
419 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
718 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
739 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
1071 CCIfType<[i64], CCAssignToReg<[R12, R13, R14, R15, RDI, RSI,
1142 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1150 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1184 R11, R12, R13, R14, R15, RBP,
[all …]
H A DX86RegisterInfo.td90 // D133902 stopped assigning register costs for R8-R15, which brought gain
298 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
535 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
588 R30, R31, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
594 RBX, R14, R15, R12, R13, RBP)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCTargetDesc.cpp68 InitCSKYMCRegisterInfo(Info, CSKY::R15); in createCSKYMCRegisterInfo()
H A DCSKYInstPrinter.cpp242 printRegName(O, CSKY::R15); in printRegisterList()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
H A DARCFrameLowering.cpp164 .addExternalSymbol(store_funclet_name[Last - ARC::R15]) in emitPrologue()
294 .addExternalSymbol(load_funclet_name[Last - ARC::R15]) in emitEpilogue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h303 ENTRY(R15) \
337 ENTRY(R15) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h55 #define R15 7 macro
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp88 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td302 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
324 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,

123