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Searched refs:R14 (Results 1 – 25 of 58) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp89 Register SPReg = CSKY::R14; in emitPrologue()
229 Register SPReg = CSKY::R14; in emitEpilogue()
513 Register SPReg = CSKY::R14; in eliminateCallFramePseudoInstr()
557 TII->get(Val < 0 ? CSKY::SUBI16SPSP : CSKY::ADDI16SPSP), CSKY::R14) in adjustReg()
558 .addReg(CSKY::R14, RegState::Kill) in adjustReg()
600 FrameReg = CSKY::R14; in getFrameIndexReference()
605 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14; in getFrameIndexReference()
616 FrameReg = hasBP(MF) ? getBPReg(STI) : CSKY::R14; in getFrameIndexReference()
H A DCSKYRegisterInfo.td66 def R14 : CSKYReg<14, "r14", ["sp"]>, DwarfRegNum<[14]>;
156 (sequence "R%u", 29, 30), R14, R31)> {
164 (sequence "R%u", 4, 11), R14)> {
176 def GPRSP : RegisterClass<"CSKY", [i32], 32, (add R14)> {
H A DCSKYInstrInfo16Instr.td377 let Defs = [R14];
378 let Uses = [R14, R0, R1, R2, R3, R12, R13];
386 let Defs = [R14, R0, R1, R2, R3, R12, R13];
387 let Uses = [R14];
398 let Defs = [R14];
399 let Uses = [R14];
410 let Defs = [R14];
411 let Uses = [R14];
H A DCSKYRegisterInfo.cpp42 return TFI->hasFP(MF) ? CSKY::R8 : CSKY::R14; in getFrameRegister()
63 markSuperRegs(Reserved, CSKY::R14); // sp in getReservedRegs()
H A DCSKYISelLowering.cpp160 setStackPointerRegisterToSaveRestore(CSKY::R14); in CSKYTargetLowering()
592 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
621 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); in LowerCall()
827 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass); in getRegForInlineAsmConstraint()
877 .Case("{sp}", CSKY::R14) in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
H A DMSP430RegisterInfo.cpp54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td69 def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>, DwarfRegNum<[14]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td50 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
88 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
104 def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
121 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
126 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp154 if (UseSaveRestoreFunclet && Last > ARC::R14) { in emitPrologue()
267 if (UseSaveRestoreFunclet && Last > ARC::R14) { in emitEpilogue()
361 if (MFI.hasCalls() || (UseSaveRestoreFunclet && Last > ARC::R14)) { in assignCalleeSavedSpillSlots()
407 if (UseSaveRestoreFunclet && Last > ARC::R14) { in spillCalleeSavedRegisters()
424 if (UseSaveRestoreFunclet && Last > ARC::R14) { in restoreCalleeSavedRegisters()
H A DARCRegisterInfo.td78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/freebsd/sys/cddl/dev/dtrace/arm/
H A Dregset.h44 #define REG_LINK R14
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPseudo.td194 // 2) R14, R15 and R28 are reserved for PLT handling and therefore are
204 let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
417 let Defs = [R14, R15, R28] in
420 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
423 let Defs = [R14, R15, R28, P0] in
426 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
552 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,
652 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>,
718 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
1071 CCIfType<[i64], CCAssignToReg<[R12, R13, R14, R15, RDI, RSI,
1142 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1145 def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>;
1150 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
[all …]
H A DX86RegisterInfo.td297 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
535 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
588 R30, R31, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
594 RBX, R14, R15, R12, R13, RBP)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h76 case Lanai::R14: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp68 CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
389 MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::R14)); in handleCROperand()
393 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14)); in handleCROperand()
394 MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14)); in handleCROperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
H A DLanaiRegisterInfo.cpp263 Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; } in getBaseRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCTargetDesc.cpp46 unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true); in createCSKYMCAsmInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_ldlib_asm.S253 #define mantxl R14
/freebsd/contrib/file/magic/Magdir/
H A Dcad209 # AutoCAD DWG versions R13/R14 (www.autodesk.com)
213 # AutoCAD DWG versions R12/R13/R14 (www.autodesk.com)
351 >>>>&1 search/8192 AC1014 \b, R14
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h302 ENTRY(R14) \
336 ENTRY(R14) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h54 #define R14 6 macro

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