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Searched refs:R12 (Results 1 – 25 of 72) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
H A DMSP430RegisterInfo.cpp51 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
57 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
H A DMSP430RegisterInfo.td67 def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>, DwarfRegNum<[12]>;
83 (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
H A DMSP430ISelLowering.cpp339 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
344 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
664 unsigned R12 = MSP430::R12; in LowerReturn() local
666 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Glue); in LowerReturn()
668 RetOps.push_back(DAG.getRegister(R12, PtrVT)); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp84 if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) { in copyPhysReg()
85 TmpReg = ARM::R12; in copyPhysReg()
H A DARMRegisterInfo.td93 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
235 (add (trunc GPR, 8), R12, LR, (shl GPR, 8))];
245 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
264 (add (trunc GPRnopc, 8), R12, LR, (shl GPRnopc, 8))];
285 (add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))];
332 (add (trunc rGPR, 8), R12, LR, (shl rGPR, 8))];
369 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
376 // Some pointer authentication instructions require the use of R12. When return
379 // jump cannot be from R12.
381 // implicitly use R12. When instructions that allow PAC to be placed in a
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H A DARMCallingConv.td165 // The 'nest' parameter, if any, is passed in R12.
166 CCIfNest<CCAssignToReg<[R12]>>,
349 : CalleeSavedRegs<(add LR, SP, (sub(sequence "R%u", 12, 1), R9, R12),
358 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
382 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
H A DThumb1FrameLowering.cpp354 case ARM::R12: in emitPrologue()
381 case ARM::R12: in emitPrologue()
959 .addReg(ARM::R12, RegState::Define) in popRegsFromStack()
1003 .addReg(ARM::R12, RegState::Kill) in popRegsFromStack()
H A DARMExpandPseudoInsts.cpp1300 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1305 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1344 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1346 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1347 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1351 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1352 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1357 .addReg(ARM::R12) in CMSEClearFPRegsV8()
2137 for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
2167 for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td48 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
89 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
105 def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
120 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
125 (add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6,
/freebsd/sys/cddl/dev/dtrace/arm/
H A Dregset.h45 #define REG_SP R12
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
376 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
412 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
536 // A SwiftError is passed in R12.
537 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
625 // A SwiftError is passed in R12.
626 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
697 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
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/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h228 UINT64 R12; member
299 UINT64 R12; member
503 UINT32 R12; member
768 UINT64 R12; member
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp157 StackSlotsUsedByFunclet = Last - ARC::R12; in emitPrologue()
269 StackSlotsUsedByFunclet = Last - ARC::R12; in emitEpilogue()
371 for (unsigned Which = Last; Which > ARC::R12; Which--) { in assignCalleeSavedSpillSlots()
384 if (I.getReg() > ARC::R12) in assignCalleeSavedSpillSlots()
H A DARCRegisterInfo.td78 (add R0, R1, R2, R3, R12, R13, R14, R15)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h72 case Lanai::R12: in getLanaiRegisterNumbering()
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Dfastmath2_dlib_asm.S265 #define c8001 R12
272 #define mantal_ R12
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp248 Value *R11, *R12, *R2; in getMaskedTypeForICmpPair() local
249 if (decomposeBitTestICmp(RHS, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
252 D = R12; in getMaskedTypeForICmpPair()
253 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
254 A = R12; in getMaskedTypeForICmpPair()
273 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
277 R12 = Constant::getAllOnesValue(R1->getType()); in getMaskedTypeForICmpPair()
282 D = R12; in getMaskedTypeForICmpPair()
285 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
286 A = R12; in getMaskedTypeForICmpPair()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td46 (add R3, R9, R12, R13, R14, R16, R17,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp449 Register R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; in findScratchRegister() local
457 *SR2 = R12; in findScratchRegister()
484 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) in findScratchRegister()
658 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue()
1578 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitEpilogue()
2476 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) in spillCalleeSavedRegisters()
2481 .addReg(PPC::R12, in spillCalleeSavedRegisters()
2541 unsigned MoveReg = PPC::R12; in restoreCRs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp163 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam335x-boneblue.dts265 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */
493 "EQEP_2B", /* R12 */
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h300 ENTRY(R12) \
334 ENTRY(R12) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h52 #define R12 4 macro
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h1211 case X86::R12: in isX86_64ExtendedReg()
1339 case X86::R12: in needSIB()

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