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Searched refs:QPR (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td558 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
560 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
564 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
568 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1004 : PseudoNLdSt<(outs QPR:$dst),
1005 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1008 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1009 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1055 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1080 def : Pat<(vector_insert (v8f16 QPR:$src),
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H A DARMRegisterInfo.td499 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128,
502 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)];
509 // Subset of QPR that have 32-bit SPR subregs.
511 128, (trunc QPR, 8)> {
515 // Subset of QPR that have DPR_8 and SPR_8 subregs.
517 128, (trunc QPR, 4)> {
522 // parsing assembly, since we still have to truncate the register set in the QPR
525 128, (trunc QPR, 8)>;
538 128, (interleave QPR, TuplesOE2D)> {
541 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)),
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H A DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DA15SDOptimizer.cpp69 bool QPR = false);
417 unsigned Lane, bool QPR) { in createDupLane() argument
419 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane()
421 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc27820 {"_ZN4llvm12_GLOBAL__N_1L3QPRE", "llvm::(anonymous namespace)::QPR"},