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Searched refs:Promote (Results 1 – 25 of 51) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td19 // Promote i8/i16 args to i32
32 // Promote i8/i16 args to i32
H A DLanaiISelLowering.cpp136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
138 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp75 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
90 setOperationAction(ISD::LOAD, MVT::v6f32, Promote); in AMDGPUTargetLowering()
93 setOperationAction(ISD::LOAD, MVT::v7f32, Promote); in AMDGPUTargetLowering()
96 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
99 setOperationAction(ISD::LOAD, MVT::v9f32, Promote); in AMDGPUTargetLowering()
102 setOperationAction(ISD::LOAD, MVT::v10f32, Promote); in AMDGPUTargetLowering()
[all …]
H A DSIISelLowering.cpp219 setOperationAction(Opc, MVT::bf16, Promote); in SITargetLowering()
225 setOperationAction(ISD::SELECT, MVT::bf16, Promote); in SITargetLowering()
265 setOperationAction(ISD::SELECT, MVT::i1, Promote); in SITargetLowering()
267 setOperationAction(ISD::SELECT, MVT::f64, Promote); in SITargetLowering()
275 setOperationAction(ISD::SETCC, MVT::i1, Promote); in SITargetLowering()
353 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
356 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
359 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
362 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote); in SITargetLowering()
367 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote); in SITargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFCallingConv.td18 // Promote i8/i16/i32 args to i64
36 // Promote i8/i16/i32 args to i64
H A DBPFISelLowering.cpp127 setOperationAction(ISD::BSWAP, MVT::i32, Promote); in BPFTargetLowering()
129 STI.getHasJmp32() ? Custom : Promote); in BPFTargetLowering()
141 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
143 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td31 // Promote i1/i8/i16/i32 arguments to i64.
62 // Promote i1/i8/i16/i32 arguments to i64.
79 // Promote i1/i8/i16/i32 return values to i64.
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp124 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
125 setOperationAction(ISD::BR_CC, MVT::f16, Promote); in MipsSETargetLowering()
126 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in MipsSETargetLowering()
127 setOperationAction(ISD::SELECT, MVT::f16, Promote); in MipsSETargetLowering()
128 setOperationAction(ISD::FADD, MVT::f16, Promote); in MipsSETargetLowering()
129 setOperationAction(ISD::FSUB, MVT::f16, Promote); in MipsSETargetLowering()
130 setOperationAction(ISD::FMUL, MVT::f16, Promote); in MipsSETargetLowering()
131 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
132 setOperationAction(ISD::FREM, MVT::f16, Promote); in MipsSETargetLowering()
133 setOperationAction(ISD::FMA, MVT::f16, Promote); in MipsSETargetLowering()
[all …]
H A DMipsCallingConv.td81 // Promote i8/i16 arguments to i32.
96 // Promote i1/i8/i16 return values to i32.
265 // Promote i8/i16 arguments to i32.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td119 // Promote i1/i8/i16/v1i1 arguments to i32.
122 // Promote v8i1/v16i1/v32i1 arguments to i32.
193 // Promote i1, v1i1, v8i1 arguments to i8.
196 // Promote v16i1 arguments to i16.
199 // Promote v32i1 arguments to i32.
354 // Promote all types to i32
415 // Promote all types to i64
537 // Promote i1/i8/i16/v1i1 arguments to i32.
638 // Promote i1/v1i1 arguments to i8.
713 // Promote i8/i16/i32 arguments to i64.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp65 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
66 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
67 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
121 setOperationAction(ISD::MUL, MVT::i8, Promote); in MSP430TargetLowering()
122 setOperationAction(ISD::MULHS, MVT::i8, Promote); in MSP430TargetLowering()
123 setOperationAction(ISD::MULHU, MVT::i8, Promote); in MSP430TargetLowering()
124 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote); in MSP430TargetLowering()
125 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote); in MSP430TargetLowering()
132 setOperationAction(ISD::UDIV, MVT::i8, Promote); in MSP430TargetLowering()
133 setOperationAction(ISD::UDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
[all …]
H A DMSP430CallingConv.td29 // Promote i8 arguments to i16.
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kCallingConv.td68 /// Promote i1/i8/i16 arguments to i32.
83 /// Promote i1/i8/i16 arguments to i32.
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreCallingConv.td27 // Promote i8/i16 arguments to i32.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCCallingConv.td28 // Promote i8/i16 arguments to i32.
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp475 // Promote the value if needed. in LowerCall()
1578 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1579 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1580 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1581 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1584 setOperationAction(ISD::CTPOP, MVT::i8, Promote); in HexagonTargetLowering()
1585 setOperationAction(ISD::CTPOP, MVT::i16, Promote); in HexagonTargetLowering()
1586 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in HexagonTargetLowering()
1686 setOperationAction(ISD::SELECT, VT, Promote); in HexagonTargetLowering()
1793 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
[all...]
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DScalar.cpp57 const auto &Promote = [](Scalar &a, const Scalar &b) { in PromoteToMaxType() local
73 Promote(rhs, lhs); in PromoteToMaxType()
75 Promote(lhs, rhs); in PromoteToMaxType()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td36 // Promote i32 to i64 if it has an explicit extension type.
93 // Promote i32 to i64 if it has an explicit extension type.
225 // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
/freebsd/contrib/llvm-project/clang/utils/TableGen/
H A DMveEmitter.cpp1042 Result::Ptr getCodeForArg(unsigned ArgNum, const Type *ArgType, bool Promote,
1312 bool Promote, bool Immediate) { in getCodeForArg() argument
1316 if (Promote) { in getCodeForArg()
1382 bool Promote = true; in ACLEIntrinsic() local
1385 Promote = false; in ACLEIntrinsic()
1437 ME.getCodeForArg(i, ArgType, Promote, Immediate); in ACLEIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp502 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
512 setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
513 if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote) in NVPTXTargetLowering()
634 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
635 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
636 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
747 setFP16OperationAction(Op, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
751 setBF16OperationAction(Op, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
752 if (getOperationAction(Op, MVT::bf16) == Promote) in NVPTXTargetLowering()
776 setBF16OperationAction(Op, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp74 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in XtensaTargetLowering()
75 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XtensaTargetLowering()
76 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h201 Promote, // This operation should be executed in a larger type. enumerator
1344 getOperationAction(Op, VT) == Promote);
1359 getOperationAction(Op, VT) == Promote);
1608 assert(Action != Promote && "Can't promote condition code!"); in getCondCodeAction()
1627 assert(getOperationAction(Op, VT) == Promote && in getTypeToPromoteTo()
1646 getOperationAction(Op, NVT) == Promote); in getTypeToPromoteTo()
2691 setOperationAction(Opc, OrigVT, Promote); in setOperationPromotedToType()
2697 setOperationAction(Op, OrigVT, Promote); in setOperationPromotedToType()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcCallingConv.td105 // - Promote to integer or floating point registers depending on type.
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp81 setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp166 void Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results);
538 case TargetLowering::Promote: in LegalizeOp()
542 Promote(Node, ResultVals); in LegalizeOp()
664 void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) { in Promote() function in VectorLegalizer

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