| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 78 Register DstReg, Register PrevReg,
165 Register DstReg, Register PrevReg, Register CurReg) { in buildMergeLaneMasks() argument
169 Register PrevRegCopy = buildRegCopyToLaneMask(PrevReg); in buildMergeLaneMasks()
|
| H A D | SILowerI1Copies.cpp | 79 Register DstReg, Register PrevReg,
856 Register DstReg, Register PrevReg, in buildMergeLaneMasks() argument
859 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal); in buildMergeLaneMasks()
880 PrevMaskedReg = PrevReg; in buildMergeLaneMasks()
884 .addReg(PrevReg) in buildMergeLaneMasks()
|
| H A D | SILowerI1Copies.h | 94 Register PrevReg, Register CurReg) = 0;
|
| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/cert/ |
| H A D | InvalidPtrChecker.cpp | 191 const MemRegion *PrevReg = *Reg; in postPreviousReturnInvalidatingCall() local
192 State = State->add<InvalidMemoryRegions>(PrevReg); in postPreviousReturnInvalidatingCall()
193 Note = C.getNoteTag([this, PrevReg, FD](PathSensitiveBugReport &BR, in postPreviousReturnInvalidatingCall()
195 if (!BR.isInteresting(PrevReg) || &BR.getBugType() != &InvalidPtrBugType) in postPreviousReturnInvalidatingCall()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1017 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
1018 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) { in defineLiveThroughVirtReg()
1019 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
1021 freePhysReg(PrevReg); in defineLiveThroughVirtReg()
1027 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
1029 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
|
| H A D | ModuloSchedule.cpp | 566 unsigned PrevReg = 0; in generateExistingPhis() local
568 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
570 NewReg, PrevReg); in generateExistingPhis()
1147 unsigned PrevReg) { in rewriteScheduledInstr() argument
1172 if (PrevReg && InProlog) in rewriteScheduledInstr()
1173 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1174 else if (PrevReg && !isLoopCarried(*Phi) && in rewriteScheduledInstr()
1176 ReplaceReg = PrevReg; in rewriteScheduledInstr()
|
| H A D | MachinePipeliner.cpp | 2629 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
2630 if (!PrevReg) in canUseLastOffsetValue()
2634 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg); in canUseLastOffsetValue()
2659 NewBase = PrevReg; in canUseLastOffsetValue()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 233 unsigned NewReg, unsigned PrevReg = 0);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 677 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
690 PrevReg = MCRegOp; in expandSET()
713 TmpInst.addOperand(PrevReg); in expandSET()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4425 unsigned PrevReg = FirstReg; in tryParseMatrixTileList() local
4444 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg))) in tryParseMatrixTileList()
4454 PrevReg = Reg; in tryParseMatrixTileList()
4517 int64_t PrevReg = FirstReg; in tryParseVectorList() local
4535 (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg); in tryParseVectorList()
4558 getContext().getRegisterInfo()->getEncodingValue(PrevReg); in tryParseVectorList()
4569 PrevReg = Reg; in tryParseVectorList()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1434 int PrevReg = *RegList.List->begin(); in isRegList16() local
1437 if ( Reg != PrevReg + 1) in isRegList16()
1439 PrevReg = Reg; in isRegList16()
6853 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6872 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6879 PrevReg = TmpReg; in parseRegisterList()
6886 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6897 if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6916 PrevReg = RegNo; in parseRegisterList()
|