| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/cert/ |
| H A D | InvalidPtrChecker.cpp | 191 const MemRegion *PrevReg = *Reg; in postPreviousReturnInvalidatingCall() local
192 State = State->add<InvalidMemoryRegions>(PrevReg); in postPreviousReturnInvalidatingCall()
193 Note = C.getNoteTag([this, PrevReg, FD](PathSensitiveBugReport &BR, in postPreviousReturnInvalidatingCall()
195 if (!BR.isInteresting(PrevReg) || &BR.getBugType() != &InvalidPtrBugType) in postPreviousReturnInvalidatingCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 76 Register DstReg, Register PrevReg,
166 Register DstReg, Register PrevReg, Register CurReg) { in buildMergeLaneMasks() argument
170 Register PrevRegCopy = buildRegCopyToLaneMask(PrevReg); in buildMergeLaneMasks()
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| H A D | SILowerI1Copies.cpp | 58 Register DstReg, Register PrevReg,
787 Register DstReg, Register PrevReg, in buildMergeLaneMasks() argument
790 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal); in buildMergeLaneMasks()
811 PrevMaskedReg = PrevReg; in buildMergeLaneMasks()
815 .addReg(PrevReg) in buildMergeLaneMasks()
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| H A D | SILowerI1Copies.h | 100 Register PrevReg, Register CurReg) = 0;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1041 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
1042 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) { in defineLiveThroughVirtReg()
1043 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
1045 freePhysReg(PrevReg); in defineLiveThroughVirtReg()
1051 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
1053 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
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| H A D | ModuloSchedule.cpp | 574 Register PrevReg; in generateExistingPhis() local
576 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
578 NewReg, PrevReg); in generateExistingPhis()
1165 Register PrevReg) { in rewriteScheduledInstr() argument
1190 if (PrevReg && InProlog) in rewriteScheduledInstr()
1191 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1192 else if (PrevReg && !isLoopCarried(*Phi) && in rewriteScheduledInstr()
1194 ReplaceReg = PrevReg; in rewriteScheduledInstr()
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| H A D | MachinePipeliner.cpp | 2925 Register PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
2926 if (!PrevReg) in canUseLastOffsetValue()
2930 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg); in canUseLastOffsetValue()
2955 NewBase = PrevReg; in canUseLastOffsetValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 699 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
712 PrevReg = MCRegOp; in expandSET()
735 TmpInst.addOperand(PrevReg); in expandSET()
758 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSETSW() local
773 PrevReg = MCRegOp; in expandSETSW()
784 .addReg(PrevReg.getReg()) in expandSETSW()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 233 Register NewReg, Register PrevReg = Register());
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1386 int PrevReg = *RegList.List->begin(); in isRegList16() local
1389 if ( Reg != PrevReg + 1) in isRegList16()
1391 PrevReg = Reg; in isRegList16()
6847 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6866 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6873 PrevReg = TmpReg; in parseRegisterList()
6880 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6891 if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6910 PrevReg = RegNo; in parseRegisterList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4556 unsigned PrevReg = FirstReg; in tryParseMatrixTileList() local
4575 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg))) in tryParseMatrixTileList()
4585 PrevReg = Reg; in tryParseMatrixTileList()
4648 MCRegister PrevReg = FirstReg; in tryParseVectorList() local
4666 (PrevReg < Reg) ? (Reg - PrevReg) : (NumRegs - (PrevReg - Reg)); in tryParseVectorList()
4689 getContext().getRegisterInfo()->getEncodingValue(PrevReg); in tryParseVectorList()
4700 PrevReg = Reg; in tryParseVectorList()
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