Searched refs:PostRA (Results 1 – 19 of 19) sorted by relevance
20 enum class SchedulingPhase { Initial, PreRAReentry, PostRA }; enumerator
1518 if (Phase != AMDGPU::SchedulingPhase::PostRA) in shouldApplyStrategy()1520 if (Phase != AMDGPU::SchedulingPhase::PostRA && !analyzeDAG(TII)) in shouldApplyStrategy()1577 bool IsPostRA = Phase == AMDGPU::SchedulingPhase::PostRA; in applyIGLPStrategy()
1155 DAG->addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA)); in createPostMachineScheduler()
2142 addMutation(createIGroupLPDAGMutation(AMDGPU::SchedulingPhase::PostRA)); in schedule()
3560 bool PostRA = !MRI->isSSA(); in foldFrameOffset() local3564 if (!PostRA) in foldFrameOffset()3771 bool PostRA = !MRI->isSSA(); in convertToImmediateForm() local3805 bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA); in convertToImmediateForm()3966 ImmInstrInfo &III, bool PostRA) const { in instrHasImmForm()4321 if (PostRA) { in instrHasImmForm()4335 if (PostRA) { in instrHasImmForm()4353 if (PostRA) { in instrHasImmForm()4367 if (PostRA) { in instrHasImmForm()4596 bool PostRA = !MRI->isSSA(); in simplifyToLI() local[all …]
762 bool PostRA) const;
1573 bool PostRA = MRI.getNumVirtRegs() == 0; in attemptDebugCopyProp() local1582 if (arePhysRegs != PostRA) in attemptDebugCopyProp()1587 if (!PostRA) in attemptDebugCopyProp()1596 if (PostRA && Reg != DstMO->getReg()) in attemptDebugCopyProp()
46 // The direction of PostRA scheduling.
25 let PostRAScheduler = 1; // Use PostRA scheduler.
29 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
23 let PostRAScheduler = 1; // Using PostRA sched.
24 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
22 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
25 let PostRAScheduler = 1; // Using PostRA sched.
24 let PostRAScheduler = 1; // Using PostRA sched.
20 let PostRAScheduler = 1; // Using PostRA sched.
15 // required until SD and PostRA schedulers are replaced by MachineScheduler.2177 // Define VLDM/VSTM PostRA Resources.2195 // VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a
15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
1839 // during ISelLowering, which produces the PostRA version of this instruction.