Searched refs:PhiReg (Results 1 – 4 of 4) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETPAndVPTOptimisationsPass.cpp | 356 Register PhiReg = LoopPhi->getOperand(0).getReg(); in MergeLoopEnd() local
382 if (!CheckUsers(PhiReg, {LoopDec}, MRI) || in MergeLoopEnd()
396 MRI->constrainRegClass(PhiReg, &ARM::GPRlrRegClass); in MergeLoopEnd()
422 .addReg(PhiReg) in MergeLoopEnd()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1682 Register PhiReg = MI.getOperand(0).getReg(); in moveStageBetweenBlocks() local
1686 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
2439 Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); in generatePhi() local
2441 TII->get(TargetOpcode::PHI), PhiReg) in generatePhi()
2446 PhiVRMap[UnrollNum][OrigReg] = PhiReg; in generatePhi()
2482 Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); in mergeRegUsesAfterPipeline() local
2484 TII->get(TargetOpcode::PHI), PhiReg) in mergeRegUsesAfterPipeline()
2491 MO->setReg(PhiReg); in mergeRegUsesAfterPipeline()
2493 if (!LIS.hasInterval(PhiReg)) in mergeRegUsesAfterPipeline()
2494 LIS.createEmptyInterval(PhiReg); in mergeRegUsesAfterPipeline()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1622 Register PhiReg = Phi->getOperand(i).getReg(); in fixupInductionVariable() local
1623 MachineInstr *DI = MRI->getVRegDef(PhiReg); in fixupInductionVariable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4463 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
4478 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg) in emitLoadM0FromVGPRLoop()
4553 unsigned InitResultReg, unsigned PhiReg, int Offset, in loadM0FromVGPR() argument
4582 InitResultReg, DstReg, PhiReg, TmpExec, in loadM0FromVGPR()
4710 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
4716 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()
4815 Register PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst() local
4818 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset, in emitIndirectDst()
4827 .addReg(PhiReg) in emitIndirectDst()
4835 .addReg(PhiReg) in emitIndirectDst()
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