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Searched refs:Pat (Results 1 – 25 of 158) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
24 def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),
26 def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),
28 def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),
30 def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2),
32 def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2),
[all …]
H A DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
16 : Pat <(IntID I32:$Rs, I32:$Rt),
20 : Pat <(IntID I32:$Rs, I64:$Rt),
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
34 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
[all …]
H A DHexagonPatternsHVX.td126 def: Pat<(ResType (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
128 def: Pat<(ResType (Load (IsOrAdd (i32 AddrFI:$fi), ImmPred:$Off))),
130 def: Pat<(ResType (Load AddrFI:$fi)), (ResType (MI AddrFI:$fi, 0))>;
135 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),
137 def: Pat<(ResType (Load I32:$Rt)),
145 def: Pat<(ResType (Load (HexagonCP tconstpool:$Addr))),
147 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$Addr))),
162 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
164 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
197 def: Pat<(Store Value:$Vs, (add (i32 AddrFI:$fi), ImmPred:$Off)),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
32 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
34 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
41 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
[all …]
H A DHexagonPatterns.td111 def: Pat<(v8i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
112 def: Pat<(v4i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
113 def: Pat<(v2i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
115 def: Pat<(v8i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;
116 def: Pat<(v4i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;
117 def: Pat<(v2i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;
294 def: Pat<(IsOrAdd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
331 : Pat<(ResVT (Op RegPred:$Rs)), (MI RegPred:$Rs)>;
335 : Pat<(ResType (Op RegPred:$Rs, ImmPred:$I)),
340 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
[all …]
H A DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
31 def : Pat <(v64i1 (bitconvert (v32i16 HvxVR:$src1))),
34 def : Pat <(v64i1 (bitconvert (v64i8 HvxVR:$src1))),
37 def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
40 def : Pat <(v32i16 (bitconvert (v64i1 HvxQR:$src1))),
43 def : Pat <(v64i8 (bitconvert (v64i1 HvxQR:$src1))),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrIntrinsicVL.gen.td1 def : Pat<(int_ve_vl_vld_vssl i64:$sy, i64:$sz, i32:$vl), (VLDrrl i64:$sy, i64:$sz, i32:$vl)>;
2 def : Pat<(int_ve_vl_vld_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDrrl_v i64:$sy, i64:$sz,…
3 def : Pat<(int_ve_vl_vld_vssl simm7:$I, i64:$sz, i32:$vl), (VLDirl (LO7 $I), i64:$sz, i32:$vl)>;
4 def : Pat<(int_ve_vl_vld_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDirl_v (LO7 $I), i64:$s…
5 def : Pat<(int_ve_vl_vldnc_vssl i64:$sy, i64:$sz, i32:$vl), (VLDNCrrl i64:$sy, i64:$sz, i32:$vl)>;
6 def : Pat<(int_ve_vl_vldnc_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCrrl_v i64:$sy, i64:…
7 def : Pat<(int_ve_vl_vldnc_vssl simm7:$I, i64:$sz, i32:$vl), (VLDNCirl (LO7 $I), i64:$sz, i32:$vl)>;
8 def : Pat<(int_ve_vl_vldnc_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCirl_v (LO7 $I), i6…
9 def : Pat<(int_ve_vl_vldu_vssl i64:$sy, i64:$sz, i32:$vl), (VLDUrrl i64:$sy, i64:$sz, i32:$vl)>;
10 def : Pat<(int_ve_vl_vldu_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDUrrl_v i64:$sy, i64:$s…
[all …]
H A DVEInstrPatternsVec.td19 def: Pat<(i64 (repl_f32 f32:$val)),
23 def: Pat<(i64 (repl_i32 i32:$val)),
34 def : Pat<(v256i1 (load ADDRrii:$addr)),
36 def : Pat<(v512i1 (load ADDRrii:$addr)),
38 def : Pat<(store v256i1:$vx, ADDRrii:$addr),
40 def : Pat<(store v512i1:$vx, ADDRrii:$addr),
46 def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
50 def : Pat<(v32 (vec_broadcast s32:$sy, i32:$vl)),
57 def : Pat<(v64 (vec_broadcast (s64 ImmOp:$sy), i32:$vl)),
61 def : Pat<(v64 (vec_broadcast s64:$sy, i32:$vl)),
[all …]
H A DVEInstrIntrinsicVL.td6 def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)),
10 def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)),
18 def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)),
21 def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)),
24 def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)),
27 def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)),
31 def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
33 def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
39 def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
41 def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td17 def : Pat<(atomic_fence (timm), 0), (MEMBARRIER)>;
18 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
19 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
54 def : Pat<(acquiring_load<atomic_load_azext_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
56 def : Pat<(acquiring_load<atomic_load_azext_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
58 def : Pat<(acquiring_load<atomic_load_nonext_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
60 def : Pat<(acquiring_load<atomic_load_nonext_64> GPR64sp:$ptr), (LDAPRX GPR64sp:$ptr)>;
64 def : Pat<(seq_cst_load<atomic_load_azext_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
65 def : Pat<(acquiring_load<atomic_load_azext_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
66 def : Pat<(relaxed_load<atomic_load_azext_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
[all …]
H A DAArch64InstrInfo.td1406 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
1409 def : Pat<(AArch64LOADgot texternalsym:$addr),
1412 def : Pat<(AArch64LOADgot tconstpool:$addr),
1653 …def : Pat<(v4i32 (partial_reduce_umla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS…
1655 …def : Pat<(v4i32 (partial_reduce_smla (v4i32 V128:$Acc), (v16i8 V128:$MulLHS), (v16i8 V128:$MulRHS…
1657 def : Pat<(v2i32 (partial_reduce_umla (v2i32 V64:$Acc), (v8i8 V64:$MulLHS), (v8i8 V64:$MulRHS))),
1659 def : Pat<(v2i32 (partial_reduce_smla (v2i32 V64:$Acc), (v8i8 V64:$MulLHS), (v8i8 V64:$MulRHS))),
1675 def : Pat<(concat_vectors (v4bf16 V64:$Rd), (any_fpround (v4f32 V128:$Rn))),
1682 def : Pat<(v2f32 (int_aarch64_neon_bfdot
1732 def : Pat<(v2i32 (partial_reduce_sumla v2i32:$Acc, v8i8:$LHS, v8i8:$RHS)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrTBM.td79 def : Pat<(and GR64:$src, AndMask64:$mask),
82 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
92 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
94 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
97 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
99 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
103 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
105 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
108 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
110 def : Pat<(an
[all...]
H A DX86InstrVecCompiler.td10 // compiler, as well as Pat patterns used during instruction selection.
20 def : Pat<(f16 (extractelt (v8f16 VR128:$src), (iPTR 0))),
22 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
24 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
30 def : Pat<(f16 (extractelt (v8f16 VR128X:$src), (iPTR 0))),
32 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
34 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
39 def : Pat<(v8f16 (scalar_to_vector FR16:$src)),
42 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
45 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
[all …]
H A DX86InstrCompiler.td10 // as well as Pat patterns used during instruction selection.
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
325 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
326 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
327 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
344 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
345 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
370 def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
375 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td44 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
46 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
48 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
50 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
56 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty 0))), (SLTIU GPR:$rs1, 1)>;
57 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
59 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty GPR:$rs2))),
61 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty 0))), (SLTU (XLenVT X0), GPR:$rs1)>;
62 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
64 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty GPR:$rs2))),
[all …]
H A DRISCVInstrInfoZfh.td294 def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;
296 def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;
297 def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
299 def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
303 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))),
305 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
309 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
313 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3))),
317 def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3)),
321 def : Pat<(f16 (any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3))),
[all …]
H A DRISCVInstrInfoD.td248 def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>;
249 def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>;
256 def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>;
257 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>;
264 def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_S_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
265 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_IN32X FPR32INX:$rs1, FRM_RNE)>;
281 def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>;
283 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
284 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
286 def : Pat<(riscv_fclass FPR64:$rs1), (FCLASS_D $rs1)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td278 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;
279 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;
2483 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2488 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
2492 def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor_be v16i8:$a,
2499 def : Pat<(v4i32 (vnot v4i32:$A)),
2501 def : Pat<(v4i32 (or (and (vnot v4i32:$C), v4i32:$A),
2505 def : Pat<(f64 (fpimm0neg)),
2508 def : Pat<(f64 (nzFPImmExactInti5:$A)),
2513 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
[all …]
H A DPPCInstrHTM.td97 def : Pat<(int_ppc_tbegin i32:$R),
100 def : Pat<(int_ppc_tend i32:$R),
103 def : Pat<(int_ppc_tabort i32:$R),
106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
118 def : Pat<(int_ppc_tcheck),
121 def : Pat<(int_ppc_treclaim i32:$RA),
124 def : Pat<(int_ppc_trechkpt),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstr64Bit.td21 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
22 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
39 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
40 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
42 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
43 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
64 def : Pat<(i64 0), (COPY (i64 G0))>,
72 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
73 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
79 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td1288 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))),
1290 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))),
1292 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))),
1294 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))),
1299 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))),
1301 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))),
1306 def : Pat<(OpNode (v16i8 LSX128:$vj), (v16i8 LSX128:$vk)),
1308 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),
1310 def : Pat<(OpNode (v4i32 LSX128:$vj), (v4i32 LSX128:$vk)),
1312 def : Pat<(OpNode (v2i64 LSX128:$vj), (v2i64 LSX128:$vk)),
[all …]
H A DLoongArchLASXInstrInfo.td1106 def : Pat<(v32i8 (OpNode (v32i8 LASX256:$xj))),
1108 def : Pat<(v16i16 (OpNode (v16i16 LASX256:$xj))),
1110 def : Pat<(v8i32 (OpNode (v8i32 LASX256:$xj))),
1112 def : Pat<(v4i64 (OpNode (v4i64 LASX256:$xj))),
1117 def : Pat<(v8f32 (OpNode (v8f32 LASX256:$xj))),
1119 def : Pat<(v4f64 (OpNode (v4f64 LASX256:$xj))),
1124 def : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 LASX256:$xk)),
1126 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 LASX256:$xk)),
1128 def : Pat<(OpNode (v8i32 LASX256:$xj), (v8i32 LASX256:$xk)),
1130 def : Pat<(OpNode (v4i64 LASX256:$xj), (v4i64 LASX256:$xk)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrCompiler.td11 /// as well as Pat patterns used during instruction selection.
19 def : Pat<(i32 (MxWrapper tconstpool :$src)), (MOV32ri tconstpool :$src)>;
20 def : Pat<(i32 (MxWrapper tglobaladdr :$src)), (MOV32ri tglobaladdr :$src)>;
21 def : Pat<(i32 (MxWrapper texternalsym :$src)), (MOV32ri texternalsym :$src)>;
22 def : Pat<(i32 (MxWrapper tjumptable :$src)), (MOV32ri tjumptable :$src)>;
23 def : Pat<(i32 (MxWrapper tblockaddress :$src)), (MOV32ri tblockaddress :$src)>;
25 def : Pat<(add MxDRD32:$src, (MxWrapper tconstpool:$opd)),
27 def : Pat<(add MxARD32:$src, (MxWrapper tjumptable:$opd)),
29 def : Pat<(add MxARD32:$src, (MxWrapper tglobaladdr :$opd)),
31 def : Pat<(add MxARD32:$src, (MxWrapper texternalsym:$opd)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td109 def : Pat<(f32 (load constpool:$src)), (f2FLRW_S (to_tconstpool tconstpool:$src))>, Requires<[HasFPUv3_SF]>;
110 def : Pat<(f64 (load constpool:$src)), (f2FLRW_D (to_tconstpool tconstpool:$src))>, Requires<[HasFPUv3_DF]>;
213 def : Pat<(f32 (fmul (fneg FPR32Op:$vrx), FPR32Op:$vry)),
217 def : Pat<(f64 (fmul (fneg FPR64Op:$vrx), FPR64Op:$vry)),
250 def : Pat<(i32 (fp_to_sint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
251 def : Pat<(i32 (fp_to_uint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
252 def : Pat<(i32 (fp_to_sint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
253 def : Pat<(i32 (fp_to_uint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
254 def : Pat<(i32 (fp_to_sint (ffloor FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
255 def : Pat<(i3
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DGlobalISelCombinerEmitter.cpp157 const Pattern *Pat = nullptr; member in __anon569e2aa20111::PrettyStackTraceEmit
160 PrettyStackTraceEmit(const Record &Def, const Pattern *Pat = nullptr) in PrettyStackTraceEmit() argument
161 : Def(Def), Pat(Pat) {} in PrettyStackTraceEmit()
171 if (Pat) in print()
172 OS << " [" << Pat->getKindName() << " '" << Pat->getName() << "']"; in print()
317 for (auto *Pat : ApplyPats) { in propagateAndInferTypes() local
318 for (unsigned K = 0; K < Pat->operands_size(); ++K) { in propagateAndInferTypes()
319 auto &Op = Pat->getOperand(K); in propagateAndInferTypes()
335 inferNamedOperandType(*Pat, Op.getOperandName(), TECs)) { in propagateAndInferTypes()
347 if (PatternType Ty = inferImmediateType(*Pat, K, TECs)) { in propagateAndInferTypes()
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