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Searched refs:PartTy (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp558 Register SrcReg, LLT SrcTy, LLT PartTy, in buildCopyToRegs() argument
561 assert(SrcTy != PartTy && "identical part types shouldn't reach here"); in buildCopyToRegs()
563 const TypeSize PartSize = PartTy.getSizeInBits(); in buildCopyToRegs()
565 if (PartTy.isVector() == SrcTy.isVector() && in buildCopyToRegs()
566 PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) { in buildCopyToRegs()
572 if (SrcTy.isVector() && !PartTy.isVector() && in buildCopyToRegs()
581 if (SrcTy.isVector() && PartTy.isVector() && in buildCopyToRegs()
582 PartTy.getSizeInBits() == SrcTy.getSizeInBits() && in buildCopyToRegs()
584 PartTy.getElementCount())) { in buildCopyToRegs()
591 LLT GCDTy = getGCDType(SrcTy, PartTy); in buildCopyToRegs()
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H A DLegalizerHelper.cpp164 LLT ResultTy, LLT PartTy, in insertParts() argument
176 if (PartTy.isVector()) in insertParts()
192 LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy); in insertParts()
5261 LLT PartTy = MRI.getType(VecParts[PartIdx]); in fewerElementsVectorExtractInsertVectorElt() local
5265 PartTy, VecParts[PartIdx], InsertVal, NewIdx); in fewerElementsVectorExtractInsertVectorElt()
5343 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, in reduceLoadStoreWidth()
5346 unsigned PartSize = PartTy.getSizeInBits(); in reduceLoadStoreWidth()
5355 MF.getMachineMemOperand(&MMO, ByteOffset, PartTy); in reduceLoadStoreWidth()
5358 Register Dst = MRI.createGenericVirtualRegister(PartTy); in reduceLoadStoreWidth()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalizeHelper.cpp73 for (LLT PartTy : LLTBreakdown) { in splitLoad() local
81 auto *OffsetMMO = MF.getMachineMemOperand(&BaseMMO, ByteOffset, PartTy); in splitLoad()
82 auto LoadPart = B.buildLoad({DstRB, PartTy}, BasePlusOffset, *OffsetMMO); in splitLoad()
84 ByteOffset += PartTy.getSizeInBytes(); in splitLoad()
H A DAMDGPURegisterBankInfo.cpp897 LLT PartTy = LLT::scalar(PartSize); in executeInWaterfallLoop() local
906 auto UnmergeOp = B.buildUnmerge(PartTy, OpReg); in executeInWaterfallLoop()
907 auto UnmergeCurrentLane = B.buildUnmerge(PartTy, CurrentLaneReg); in executeInWaterfallLoop()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h207 LLT PartTy, ArrayRef<Register> PartRegs,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DSROA.cpp4664 auto *PartTy = Type::getIntNTy(LI->getContext(), PartSize * 8); in presplitLoadsAndStores() local
4668 PartTy, in presplitLoadsAndStores()
4805 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8); in presplitLoadsAndStores() local
4817 PartTy, in presplitLoadsAndStores()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3220 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) in LowerUnalignedLoad() local
3223 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand()); in LowerUnalignedLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1519 Type *PartTy = PartVT.getTypeForEVT(*DAG.getContext()); in ExpandInsertToVectorThroughStack() local
1520 Align PartAlignment = DAG.getDataLayout().getPrefTypeAlign(PartTy); in ExpandInsertToVectorThroughStack()