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Searched refs:PMULL (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td587 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v8i8|v16i8)")>;
588 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>;
H A DAArch64SchedA57.td411 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
412 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
H A DAArch64SchedThunderX2T99.td569 def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL")>;
1281 def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^PMULL(v8i8|v16i8)")>;
1282 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>;
H A DAArch64SchedThunderX3T110.td829 def : InstRW<[THX3T110Write_4Cyc_F0123], (instregex "^PMULL")>;
1389 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v8i8|v16i8)")>;
1390 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v1i64|v2i64)")>;
H A DAArch64ISelLowering.h332 PMULL, enumerator
H A DAArch64SchedFalkorDetails.td738 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^PMULL(v8i8|v16i8)$")>;
751 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^PMULL(v1i64|v2i64)$")>;
H A DAArch64SchedA64FX.td731 def : InstRW<[A64FXWrite_8Cyc_GI0], (instregex "^PMULL")>;
1405 def : InstRW<[A64FXWrite_8Cyc_GI03], (instregex "^PMULL(v8i8|v16i8)")>;
1406 def : InstRW<[A64FXWrite_8Cyc_GI03], (instregex "^PMULL(v1i64|v2i64)")>;
H A DAArch64SchedExynosM3.td869 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
H A DAArch64Features.td664 "CPU fuses AES/PMULL and EOR operations">;
H A DAArch64SchedAmpere1.td702 def : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^PMUL", "^PMULL")>;
H A DAArch64SchedAmpere1B.td664 def : InstRW<[Ampere1BWrite_2cyc_1XY], (instregex "^PMUL", "^PMULL")>;
H A DAArch64SchedNeoverseN2.td1014 def : InstRW<[N2Write_3cyc_1V0], (instregex "^PMULL?(v8i8|v16i8)$")>;
1866 "^PMULL[BT]_ZZZ_[HDQ]$")>;
H A DAArch64SchedNeoverseV2.td1506 def : InstRW<[V2Write_3cyc_1V23], (instregex "^PMULL?(v8i8|v16i8)$")>;
2384 "^PMULL[BT]_ZZZ_[HDQ]")>;
H A DAArch64SchedA510.td945 def : InstRW<[CortexA510Write<9, CortexA510UnitVMC>], (instregex "^PMULL[BT]_ZZZ_[HDQ]")>;
H A DAArch64SchedNeoverseV1.td865 def : InstRW<[V1Write_3c_1V01], (instregex "^PMULL?v(8|16)i8$")>;
H A DAArch64ISelLowering.cpp2753 MAKE_CASE(AArch64ISD::PMULL) in getTargetNodeName()
5696 return DAG.getNode(AArch64ISD::PMULL, dl, Op.getValueType(), LHS, RHS); in LowerINTRINSIC_WO_CHAIN()
21280 return DAG.getNode(AArch64ISD::PMULL, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
25411 case AArch64ISD::PMULL: in PerformDAGCombine()
H A DAArch64InstrInfo.td842 def AArch64pmull : SDNode<"AArch64ISD::PMULL", SDT_AArch64mull,
6299 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull", AArch64pmull>;