1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Scott Long 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Thunderbolt 3 register definitions 29 */ 30 31 #ifndef _NHI_REG_H 32 #define _NHI_REG_H 33 34 /* Some common definitions */ 35 #define TBT_SEC_NONE 0x00 36 #define TBT_SEC_USER 0x01 37 #define TBT_SEC_SECURE 0x02 38 #define TBT_SEC_DP 0x03 39 40 #define GENMASK(h, l) (((~0U) >> (31 - (h))) ^ ((~0U) >> (31 - (l)) >> 1)) 41 42 /* PCI Vendor and Device ID's */ 43 #define VENDOR_INTEL 0x8086 44 #define DEVICE_AR_2C_NHI 0x1575 45 #define DEVICE_AR_DP_B_NHI 0x1577 46 #define DEVICE_AR_DP_C_NHI 0x15d2 47 #define DEVICE_AR_LP_NHI 0x15bf 48 #define DEVICE_ICL_NHI_0 0x8a17 49 #define DEVICE_ICL_NHI_1 0x8a0d 50 51 #define VENDOR_AMD 0x1022 52 #define DEVICE_PINK_SARDINE_0 0x1668 53 #define DEVICE_PINK_SARDINE_1 0x1669 54 55 /* * * MMIO Registers 56 * * Ring buffer registers 57 * 58 * 32 transmit and receive rings are available, with Ring 0 being the most 59 * important one. The ring descriptors are 16 bytes each, and each set of 60 * TX and RX descriptors are packed together. There are only definitions 61 * for the Ring 0 addresses, others can be directly computed. 62 */ 63 #define NHI_TX_RING_ADDR_LO 0x00000 64 #define NHI_TX_RING_ADDR_HI 0x00004 65 #define NHI_TX_RING_PICI 0x00008 66 #define TX_RING_CI_MASK GENMASK(15, 0) 67 #define TX_RING_PI_SHIFT 16 68 #define NHI_TX_RING_SIZE 0x0000c 69 70 #define NHI_RX_RING_ADDR_LO 0x08000 71 #define NHI_RX_RING_ADDR_HI 0x08004 72 #define NHI_RX_RING_PICI 0x08008 73 #define RX_RING_CI_MASK GENMASK(15, 0) 74 #define RX_RING_PI_SHIFT 16 75 #define NHI_RX_RING_SIZE 0x0800c 76 #define RX_RING_BUF_SIZE_SHIFT 16 77 78 /* 79 * One 32-bit status register encodes one status bit per ring indicates that 80 * the watermark from the control descriptor has been reached. 81 */ 82 #define NHI_RX_RING_STATUS 0x19400 83 84 /* 85 * TX and RX Tables. These are 32 byte control fields for each ring. 86 * Only 8 bytes are controllable by the host software, the rest are a 87 * shadow copy by the controller of the current packet that's being 88 * processed. 89 */ 90 #define NHI_TX_RING_TABLE_BASE0 0x19800 91 #define TX_TABLE_INTERVAL_MASK GENMASK(23,0) /* Isoch interval 256ns */ 92 #define TX_TABLE_ITE (1 << 27) /* Isoch tx enable */ 93 #define TX_TABLE_E2E (1 << 28) /* End-to-end flow control */ 94 #define TX_TABLE_NS (1 << 29) /* PCIe No Snoop */ 95 #define TX_TABLE_RAW (1 << 30) /* Raw (1)/frame(0) mode */ 96 #define TX_TABLE_VALID (1 << 31) /* Table entry is valid */ 97 #define NHI_TX_RING_TABLE_TIMESTAMP 0x19804 98 99 #define NHI_RX_RING_TABLE_BASE0 0x29800 100 #define RX_TABLE_TX_E2E_HOPID_SHIFT (1 << 12) 101 #define RX_TABLE_E2E (1 << 28) /* End-to-end flow control */ 102 #define RX_TABLE_NS (1 << 29) /* PCIe No Snoop */ 103 #define RX_TABLE_RAW (1 << 30) /* Raw (1)/frame(0) mode */ 104 #define RX_TABLE_VALID (1 << 31) /* Table entry is valid */ 105 #define NHI_RX_RING_TABLE_BASE1 0x29804 106 #define RX_TABLE_EOF_MASK (1 << 0) 107 #define RX_TABLE_SOF_MASK (1 << 16) 108 109 /* * Interrupt Control/Status Registers 110 * Interrupt Status Register (ISR) 111 * Interrupt status for RX, TX, and Nearly Empty events, one bit per 112 * MSI-X vector. Clear on read. 113 * Only 12 bits per operation, instead of 16? I guess it relates to the 114 * number paths, advertised in the HOST_CAPS register, which is wired to 115 * 0x0c for Alpine Ridge. 116 */ 117 #define NHI_ISR0 0x37800 118 #define ISR0_TX_DESC_SHIFT 0 119 #define ISR0_RX_DESC_SHIFT 12 120 #define ISR0_RX_EMPTY_SHIFT 24 121 #define NHI_ISR1 0x37804 122 #define ISR1_RX_EMPTY_SHIFT 0 123 124 /* * Interrupt Status Clear, corresponds to ISR0/ISR1. Write Only */ 125 #define NHI_ISC0 0x37808 126 #define NHI_ISC1 0x3780c 127 128 /* * Interrupt Status Set, corresponds to ISR0/ISR1. Write Only */ 129 #define NHI_ISS0 0x37810 130 #define NHI_ISS1 0x37814 131 132 /* * Interrupt Mask, corresponds to ISR0/ISR1. Read-Write */ 133 #define NHI_IMR0 0x38200 134 #define NHI_IMR1 0x38204 135 #define IMR_TX_OFFSET 0 136 #define IMR_RX_OFFSET 12 137 #define IMR_NE_OFFSET 24 138 139 /* * Interrupt Mask Clear, corresponds to ISR0/ISR1. Write-only */ 140 #define NHI_IMC0 0x38208 141 #define NHI_IMC1 0x3820c 142 143 /* * Interrupt Mask Set, corresponds to ISR0/ISR1. Write-only */ 144 #define NHI_IMS0 0x38210 145 #define NHI_IMS1 0x38214 146 147 /* 148 * Interrupt Throttle Rate. One 32 bit register per interrupt, 149 * 16 registers for the 16 MSI-X interrupts. Interval is in 256ns 150 * increments. 151 */ 152 #define NHI_ITR0 0x38c00 153 #define ITR_INTERVAL_SHIFT 0 154 #define ITR_COUNTER_SHIFT 16 155 156 /* 157 * Interrupt Vector Allocation. 158 * There are 12 4-bit descriptors for TX, 12 4-bit descriptors for RX, 159 * and 12 4-bit descriptors for Nearly Empty. Each descriptor holds 160 * the numerical value of the MSI-X vector that will receive the 161 * corresponding interrupt. 162 * Bits 0-31 of IVR0 and 0-15 of IVR1 are for TX 163 * Bits 16-31 of IVR1 and 0-31 of IVR2 are for RX 164 * Bits 0-31 of IVR3 and 0-15 of IVR4 are for Nearly Empty 165 */ 166 #define NHI_IVR0 0x38c40 167 #define NHI_IVR1 0x38c44 168 #define NHI_IVR2 0x38c48 169 #define NHI_IVR3 0x38c4c 170 #define NHI_IVR4 0x38c50 171 #define IVR_TX_OFFSET 0 172 #define IVR_RX_OFFSET 12 173 #define IVR_NE_OFFSET 24 174 175 /* Native Host Interface Control registers */ 176 #define NHI_HOST_CAPS 0x39640 177 178 /* Host Interface Capabilities, 12.6.3.1.1 */ 179 struct nhi_host_caps { 180 uint32_t total_paths:11; 181 uint8_t reserved1:5; 182 uint8_t version_major:3; 183 uint8_t version_minor:5; 184 uint8_t reserved0:8; 185 } __packed; 186 187 /* 188 * This definition comes from the Linux driver. In the USB4 spec, this 189 * register is named Host Interface Control, and the Interrupt Autoclear bit 190 * is at bit17, not bit2. The Linux driver doesn't seem to acknowledge this. 191 */ 192 #define NHI_DMA_MISC 0x39864 193 #define DMA_MISC_INT_AUTOCLEAR (1 << 2) 194 195 /* Thunderbolt firmware mailbox registers */ 196 #define TBT_INMAILDATA 0x39900 197 198 #define TBT_INMAILCMD 0x39904 199 #define INMAILCMD_CMD_MASK 0xff 200 #define INMAILCMD_SAVE_CONNECTED 0x05 201 #define INMAILCMD_DISCONNECT_PCIE 0x06 202 #define INMAILCMD_DRIVER_UNLOAD_DISCONNECT 0x07 203 #define INMAILCMD_DISCONNECT_PORTA 0x10 204 #define INMAILCMD_DISCONNECT_PORTB 0x11 205 #define INMAILCMD_SETMODE_CERT_TB_1ST_DEPTH 0x20 206 #define INMAILCMD_SETMODE_ANY_TB_1ST_DEPTH 0x21 207 #define INMAILCMD_SETMODE_CERT_TB_ANY_DEPTH 0x22 208 #define INMAILCMD_SETMODE_ANY_TB_ANY_DEPTH 0x23 209 #define INMAILCMD_CIO_RESET 0xf0 210 #define INMAILCMD_ERROR (1 << 30) 211 #define INMAILCMD_OPREQ (1 << 31) 212 213 #define TBT_OUTMAILCMD 0x3990c 214 #define OUTMAILCMD_STATUS_BUSY (1 << 12) 215 #define OUTMAILCMD_OPMODE_MASK 0xf00 216 #define OUTMAILCMD_OPMODE_SAFE 0x000 217 #define OUTMAILCMD_OPMODE_AUTH 0x100 218 #define OUTMAILCMD_OPMODE_ENDPOINT 0x200 219 #define OUTMAILCMD_OPMODE_CM_FULL 0x300 220 221 #define TBT_FW_STATUS 0x39944 222 #define FWSTATUS_ENABLE (1 << 0) 223 #define FWSTATUS_INVERT (1 << 1) 224 #define FWSTATUS_START (1 << 2) 225 #define FWSTATUS_CIO_RESET (1 << 30) 226 #define FWSTATUS_CM_READY (1 << 31) 227 228 /* 229 * Link Controller (LC) registers. These are in the Vendor Specific 230 * Extended Capability registers in PCICFG. 231 */ 232 #define AR_LC_MBOX_OUT 0x4c 233 #define ICL_LC_MBOX_OUT 0xf0 234 #define LC_MBOXOUT_VALID (1 << 0) 235 #define LC_MBOXOUT_CMD_SHIFT 1 236 #define LC_MBOXOUT_CMD_MASK (0x7f << LC_MBOXOUT_CMD_SHIFT) 237 #define LC_MBOXOUT_CMD_GO2SX (0x02 << LC_MBOXOUT_CMD_SHIFT) 238 #define LC_MBOXOUT_CMD_GO2SX_NOWAKE (0x03 << LC_MBOXOUT_CMD_SHIFT) 239 #define LC_MBOXOUT_CMD_SXEXIT_TBT (0x04 << LC_MBOXOUT_CMD_SHIFT) 240 #define LC_MBOXOUT_CMD_SXEXIT_NOTBT (0x05 << LC_MBOXOUT_CMD_SHIFT) 241 #define LC_MBOXOUT_CMD_OS_UP (0x06 << LC_MBOXOUT_CMD_SHIFT) 242 #define LC_MBOXOUT_DATA_SHIFT 8 243 #define SET_LC_MBOXOUT_DATA(val) ((val) << LC_MBOXOUT_DATA_SHIFT) 244 245 #define AR_LC_MBOX_IN 0x48 246 #define ICL_LC_MBOX_IN 0xec 247 #define LC_MBOXIN_DONE (1 << 0) 248 #define LC_MBOXIN_CMD_SHIFT 1 249 #define LC_MBOXIN_CMD_MASK (0x7f << LC_MBOXIN_CMD_SHIFT) 250 #define LC_MBOXIN_DATA_SHIFT 8 251 #define GET_LC_MBOXIN_DATA(val) ((val) >> LC_MBOXIN_DATA_SHIFT) 252 253 /* Other Vendor Specific registers */ 254 #define AR_VSCAP_1C 0x1c 255 #define AR_VSCAP_B0 0xb0 256 257 #define ICL_VSCAP_9 0xc8 258 #define ICL_VSCAP9_FWREADY (1 << 31) 259 #define ICL_VSCAP_10 0xcc 260 #define ICL_VSCAP_11 0xd0 261 #define ICL_VSCAP_22 0xfc 262 #define ICL_VSCAP22_FORCEPWR (1 << 1) 263 264 /* * Data structures 265 * Transmit buffer descriptor, 12.3.1. Must be aligned on a 4byte boundary. 266 */ 267 struct nhi_tx_buffer_desc { 268 uint32_t addr_lo; 269 uint32_t addr_hi; 270 uint16_t eof_len; 271 #define TX_BUFFER_DESC_LEN_MASK 0xfff 272 #define TX_BUFFER_DESC_EOF_SHIFT 12 273 uint8_t flags_sof; 274 #define TX_BUFFER_DESC_SOF_MASK 0xf 275 #define TX_BUFFER_DESC_IDE (1 << 4) /* Isoch DMA enable */ 276 #define TX_BUFFER_DESC_DONE (1 << 5) /* Descriptor Done */ 277 #define TX_BUFFER_DESC_RS (1 << 6) /* Request Status/Done */ 278 #define TX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 279 uint8_t offset; 280 uint32_t payload_time; 281 } __packed; 282 283 /* 284 * Receive buffer descriptor, 12.4.1. 4 byte aligned. This goes into 285 * the descriptor ring, but changes into the _post form when the 286 * controller uses it. 287 */ 288 struct nhi_rx_buffer_desc { 289 uint32_t addr_lo; 290 uint32_t addr_hi; 291 uint16_t reserved0; 292 uint8_t flags; 293 #define RX_BUFFER_DESC_RS (1 << 6) /* Request Status/Done */ 294 #define RX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 295 uint8_t offset; 296 uint32_t reserved1; 297 } __packed; 298 299 /* 300 * Receive buffer descriptor, after the controller fills it in 301 */ 302 struct nhi_rx_post_desc { 303 uint32_t addr_lo; 304 uint32_t addr_hi; 305 uint16_t eof_len; 306 #define RX_BUFFER_DESC_LEN_MASK 0xfff 307 #define RX_BUFFER_DESC_EOF_SHIFT 12 308 uint8_t flags_sof; 309 #define RX_BUFFER_DESC_SOF_MASK 0xf 310 #define RX_BUFFER_DESC_CRC_ERROR (1 << 4) /* CRC error (frame mode) */ 311 #define RX_BUFFER_DESC_DONE (1 << 5) /* Descriptor Done */ 312 #define RX_BUFFER_DESC_OVERRUN (1 << 6) /* Buffer overrun */ 313 #define RX_BUFFER_DESC_IE (1 << 7) /* Interrupt Enable */ 314 uint8_t offset; 315 uint32_t payload_time; 316 } __packed; 317 318 union nhi_ring_desc { 319 struct nhi_tx_buffer_desc tx; 320 struct nhi_rx_buffer_desc rx; 321 struct nhi_rx_post_desc rxpost; 322 uint32_t dword[4]; 323 }; 324 325 /* Protocol Defined Field (PDF) */ 326 #define PDF_READ 0x01 327 #define PDF_WRITE 0x02 328 #define PDF_NOTIFY 0x03 329 #define PDF_NOTIFY_ACK 0x04 330 #define PDF_HOTPLUG 0x05 331 #define PDF_XDOMAIN_REQ 0x06 332 #define PDF_XDOMAIN_RESP 0x07 333 /* Thunderbolt-only */ 334 #define PDF_CM_EVENT 0x0a 335 #define PDF_CM_REQ 0x0b 336 #define PDF_CM_RESP 0x0c 337 338 #endif /* _NHI_REG_H */ 339