| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFoldMemOffset.cpp | 38 bool foldOffset(Register OrigReg, int64_t InitialOffset,
91 Register OrigReg, int64_t InitialOffset, const MachineRegisterInfo &MRI, in foldOffset() argument
97 RegToOffsetMap[OrigReg] = InitialOffset; in foldOffset()
100 Worklist.push(OrigReg); in foldOffset()
196 if (User.getOperand(1).getReg() == OrigReg) in foldOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastPreTileConfig.cpp | 218 Register OrigReg, MachineOperand *RowMO, in reload() argument
220 int FI = getStackSpaceFor(OrigReg); in reload()
221 const TargetRegisterClass &RC = *MRI->getRegClass(OrigReg); in reload()
260 if (MO.isReg() && MO.getReg() == OrigReg) in reload()
266 LLVM_DEBUG(dbgs() << "Reloading " << printReg(OrigReg, TRI) << " into " in reload()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 2343 Register OrigReg = UseMO.getReg(); in updateInstrUse() local
2344 MachineInstr *DefInst = MRI.getVRegDef(OrigReg); in updateInstrUse()
2348 Register DefReg = OrigReg; in updateInstrUse()
2375 MRI.constrainRegClass(NewReg, MRI.getRegClass(OrigReg)); in updateInstrUse()
2379 Register SplitReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); in updateInstrUse()
2450 Register OrigReg = DefMO.getReg(); in generatePhi() local
2451 auto NewReg = KernelVRMap[UnrollNum].find(OrigReg); in generatePhi()
2457 CorrespondReg = PrologVRMap[PrologNum][OrigReg]; in generatePhi()
2459 MachineInstr *Phi = getLoopPhiUser(OrigReg, OrigKernel); in generatePhi()
2466 Register PhiReg = MRI.createVirtualRegister(MRI.getRegClass(OrigReg)); in generatePhi()
[all …]
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| H A D | TailDuplicator.cpp | 339 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg, in addSSAUpdateEntry() argument
342 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
348 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
349 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
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| H A D | RegisterBankInfo.cpp | 470 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
472 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
478 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
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| H A D | InlineSpiller.cpp | 1385 Register OrigReg = OrigLI.reg(); in isSpillCandBB() local
1386 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
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| H A D | SplitKit.cpp | 334 Register OrigReg = VRM.getOriginal(CurLI->reg()); in isOriginalEndpoint() local
335 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 553 Register OrigReg = U.getReg(); in colorChain() local
554 U.setReg(Substs[OrigReg]); in colorChain()
558 ToErase.push_back(OrigReg); in colorChain()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TailDuplicator.h | 100 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
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| H A D | ModuloSchedule.h | 416 void mergeRegUsesAfterPipeline(Register OrigReg, Register NewReg);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 737 Register OrigReg = OrigArg.Regs[0]; in lowerFormalArguments() local
740 BoolArgs.push_back({OrigReg, WideReg}); in lowerFormalArguments()
767 Register OrigReg = KV.first; in lowerFormalArguments() local
770 assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 && in lowerFormalArguments()
773 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0)); in lowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 4460 const SCEV *OrigReg; member
4463 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4473 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4523 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4526 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
4528 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4530 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg in GenerateCrossUseConstantOffsets()
4540 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg in GenerateCrossUseConstantOffsets()
4568 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4583 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1716 MCRegister OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1722 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1727 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1729 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1731 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1741 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1048 for (const auto &[OrigReg, N] : RegsToPass) { in LowerCall_32()
1049 Register Reg = isTailCall ? OrigReg : toCallerWindow(OrigReg); in LowerCall_32()
1071 for (const auto &[OrigReg, N] : RegsToPass) { in LowerCall_32()
1072 Register Reg = isTailCall ? OrigReg : toCallerWindow(OrigReg); in LowerCall_32()
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