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Searched refs:OpVT (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRuntimeLibcallUtil.h33 LLVM_ABI Libcall getFPEXT(EVT OpVT, EVT RetVT);
37 LLVM_ABI Libcall getFPROUND(EVT OpVT, EVT RetVT);
41 LLVM_ABI Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
45 LLVM_ABI Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
49 LLVM_ABI Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
53 LLVM_ABI Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp120 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { in getFPEXT() argument
121 if (OpVT == MVT::f16) { in getFPEXT()
130 } else if (OpVT == MVT::f32) { in getFPEXT()
137 } else if (OpVT == MVT::f64) { in getFPEXT()
142 } else if (OpVT == MVT::f80) { in getFPEXT()
145 } else if (OpVT == MVT::bf16) { in getFPEXT()
155 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { in getFPROUND() argument
157 if (OpVT == MVT::f32) in getFPROUND()
159 if (OpVT == MVT::f64) in getFPROUND()
161 if (OpVT == MVT::f80) in getFPROUND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp67 EVT OpVT = N->getOperand(0).getValueType(); in verifyTargetNode() local
68 assert(OpVT.isVector() && VT.isVector() && OpVT.isInteger() && in verifyTargetNode()
70 assert(OpVT.getSizeInBits() == VT.getSizeInBits() && in verifyTargetNode()
72 assert(OpVT.getVectorElementCount() == VT.getVectorElementCount() * 2 && in verifyTargetNode()
H A DAArch64ISelLowering.cpp2139 EVT OpVT) const { in shouldExpandGetActiveLaneMask()
2148 (OpVT != MVT::i32 && OpVT != MVT::i64)))) in shouldExpandGetActiveLaneMask()
2153 if (OpVT.getFixedSizeInBits() > 64) in shouldExpandGetActiveLaneMask()
5107 EVT OpVT = Op.getValueType(); in LowerBITCAST() local
5110 if (useSVEForFixedLengthVectorVT(OpVT)) in LowerBITCAST()
5113 if (OpVT.isScalableVector()) { in LowerBITCAST()
5114 assert(isTypeLegal(OpVT) && "Unexpected result type!"); in LowerBITCAST()
5118 assert(OpVT.isFloatingPoint() && !ArgVT.isFloatingPoint() && in LowerBITCAST()
5126 if (OpVT.getVectorElementCount() != ArgVT.getVectorElementCount()) in LowerBITCAST()
5132 return getSVESafeBitCast(OpVT, ExtResult, DAG); in LowerBITCAST()
[all …]
H A DAArch64ISelLowering.h503 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp199 EVT OpVT = N->getOperand(0 + Offset).getValueType(); in SoftenFloatRes_Unary() local
200 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); in SoftenFloatRes_Unary()
644 EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType(); in SoftenFloatRes_FP_EXTEND() local
645 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); in SoftenFloatRes_FP_EXTEND()
696 EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType(); in SoftenFloatRes_FP_ROUND() local
697 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); in SoftenFloatRes_FP_ROUND()
1455 EVT OpVT = N->getOperand(0 + Offset).getValueType(); in SoftenFloatOp_Unary() local
1456 CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); in SoftenFloatOp_Unary()
1470 EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType(); in SoftenFloatOp_LROUND() local
1471 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT, in SoftenFloatOp_LROUND()
[all …]
H A DTargetLowering.cpp4159 EVT OpVT = N0.getValueType(); in foldSetCCWithAnd() local
4160 if (N0.getOpcode() != ISD::AND || !OpVT.isInteger() || in foldSetCCWithAnd()
4167 (getBooleanContents(OpVT) == TargetLowering::UndefinedBooleanContent || in foldSetCCWithAnd()
4168 getBooleanContents(OpVT) == TargetLowering::ZeroOrOneBooleanContent)) { in foldSetCCWithAnd()
4169 unsigned NumEltBits = OpVT.getScalarSizeInBits(); in foldSetCCWithAnd()
4172 return DAG.getBoolExtOrTrunc(N0, DL, VT, OpVT); in foldSetCCWithAnd()
4184 isTypeLegal(OpVT) && N0.hasOneUse()) { in foldSetCCWithAnd()
4187 if (isTruncateFree(OpVT, NarrowVT) && isTypeLegal(NarrowVT)) { in foldSetCCWithAnd()
4212 SDValue Zero = DAG.getConstant(0, DL, OpVT); in foldSetCCWithAnd()
4213 if (isXAndYEqZeroPreferableToXAndYEqY(Cond, OpVT) && in foldSetCCWithAnd()
[all …]
H A DLegalizeVectorTypes.cpp427 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_FP_ROUND() local
430 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_FP_ROUND()
433 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_FP_ROUND()
478 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_UnaryOp() local
487 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_UnaryOp()
490 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_UnaryOp()
508 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_VecInregOp() local
509 EVT OpEltVT = OpVT.getVectorElementType(); in ScalarizeVecRes_VecInregOp()
512 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) { in ScalarizeVecRes_VecInregOp()
533 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_ADDRSPACECAST() local
[all …]
H A DSelectionDAG.cpp1555 EVT OpVT) { in getBoolExtOrTrunc() argument
1559 TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT); in getBoolExtOrTrunc()
1564 EVT OpVT = Op.getValueType(); in getZeroExtendInReg() local
1565 assert(VT.isInteger() && OpVT.isInteger() && in getZeroExtendInReg()
1567 assert(VT.isVector() == OpVT.isVector() && in getZeroExtendInReg()
1571 VT.getVectorElementCount() == OpVT.getVectorElementCount()) && in getZeroExtendInReg()
1573 assert(VT.bitsLE(OpVT) && "Not extending!"); in getZeroExtendInReg()
1574 if (OpVT == VT) in getZeroExtendInReg()
1576 APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(), in getZeroExtendInReg()
1578 return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT)); in getZeroExtendInReg()
[all …]
H A DLegalizeVectorOps.cpp330 MVT OpVT = Node->getOperand(1).getSimpleValueType(); in LegalizeOp() local
332 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
334 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
524 MVT OpVT = Node->getOperand(0).getSimpleValueType(); in LegalizeOp() local
526 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
528 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
694 MVT OpVT = Node->getOperand(0).getSimpleValueType(); in PromoteFloatVECREDUCE() local
695 assert(OpVT.isFloatingPoint() && "Expected floating point reduction!"); in PromoteFloatVECREDUCE()
696 MVT NewOpVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OpVT); in PromoteFloatVECREDUCE()
2036 MVT OpVT = LHS.getSimpleValueType(); in ExpandSETCC() local
[all …]
H A DScheduleDAGSDNodes.cpp486 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
487 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
488 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
H A DDAGCombiner.cpp6336 EVT OpVT = LL.getValueType(); in foldLogicOfSetCCs() local
6338 if (VT != getSetCCResultType(OpVT)) in foldLogicOfSetCCs()
6340 if (OpVT != RL.getValueType()) in foldLogicOfSetCCs()
6345 bool IsInteger = OpVT.isInteger(); in foldLogicOfSetCCs()
6364 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL); in foldLogicOfSetCCs()
6383 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); in foldLogicOfSetCCs()
6391 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && in foldLogicOfSetCCs()
6395 SDValue One = DAG.getConstant(1, DL, OpVT); in foldLogicOfSetCCs()
6396 SDValue Two = DAG.getConstant(2, DL, OpVT); in foldLogicOfSetCCs()
6397 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One); in foldLogicOfSetCCs()
[all …]
H A DLegalizeTypes.cpp315 EVT OpVT = Op.getValueType(); in run() local
316 switch (getTypeAction(OpVT)) { in run()
H A DInstrEmitter.cpp410 MVT OpVT = Op.getSimpleValueType(); in AddOperand() local
415 TLI->isTypeLegal(OpVT) in AddOperand()
416 ? TLI->getRegClassFor(OpVT, in AddOperand()
H A DLegalizeIntegerTypes.cpp2353 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy; in PromoteIntOp_SELECT() local
2354 Cond = PromoteTargetBoolean(Cond, OpVT); in PromoteIntOp_SELECT()
4153 EVT OpVT = Op.getValueType(); in ExpandIntRes_FP_TO_XINT() local
4156 IsSigned ? RTLIB::getFPTOSINT(OpVT, VT) : RTLIB::getFPTOUINT(OpVT, VT); in ExpandIntRes_FP_TO_XINT()
4160 CallOptions.setTypeListBeforeSoften(OpVT, VT); in ExpandIntRes_FP_TO_XINT()
6106 EVT OpVT = Op.getValueType(); in PromoteIntRes_BUILD_VECTOR() local
6111 if (OpVT.bitsLT(NOutVTElem)) { in PromoteIntRes_BUILD_VECTOR()
6116 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant) in PromoteIntRes_BUILD_VECTOR()
6181 EVT OpVT = Op.getValueType(); in PromoteIntRes_CONCAT_VECTORS() local
6182 if (getTypeAction(OpVT) == TargetLowering::TypePromoteInteger) in PromoteIntRes_CONCAT_VECTORS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4481 EVT OpVT = Op.getValueType(); in SplitOpsAndApply() local
4482 unsigned NumSubElts = OpVT.getVectorNumElements() / NumSubs; in SplitOpsAndApply()
4483 unsigned SizeSub = OpVT.getSizeInBits() / NumSubs; in SplitOpsAndApply()
4501 auto MakeBroadcastOp = [&](SDValue Op, MVT OpVT, MVT DstVT) { in getAVX512Node() argument
4502 unsigned OpEltSizeInBits = OpVT.getScalarSizeInBits(); in getAVX512Node()
4505 if (!OpVT.isInteger() || OpEltSizeInBits < 32 || in getAVX512Node()
4509 if (OpVT == DstVT && Op.getOpcode() != ISD::BITCAST) in getAVX512Node()
4532 MVT OpVT = Op.getSimpleValueType(); in getAVX512Node() local
4534 if (!OpVT.isVector()) in getAVX512Node()
4536 assert(OpVT == VT && "Vector type mismatch"); in getAVX512Node()
[all …]
H A DX86InstrSSE.td2264 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2273 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
2280 [(set RC:$dst, (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>,
4758 ValueType DstVT, ValueType OpVT, RegisterClass RC,
4767 [(set RC:$dst, (DstVT (OpNode (OpVT RC:$src1), RC:$src2)))]>,
4775 (DstVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))]>,
5852 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5861 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
5869 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>,
6012 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
[all …]
H A DX86InstrFMA.td391 X86MemOperand x86memop, ValueType OpVT, SDPatternOperator OpNode,
399 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, REX_W, VEX_LIG,
H A DX86ISelDAGToDAG.cpp647 EVT OpVT = N->getOperand(0).getValueType(); in INITIALIZE_PASS() local
651 OpVT = N->getOperand(1).getValueType(); in INITIALIZE_PASS()
652 if (OpVT.is256BitVector() || OpVT.is128BitVector()) in INITIALIZE_PASS()
4392 EVT OpVT = ShiftAmt.getValueType(); in tryShiftAmountMod() local
4394 SDValue AllOnes = CurDAG->getAllOnesConstant(DL, OpVT); in tryShiftAmountMod()
4395 NewShiftAmt = CurDAG->getNode(ISD::XOR, DL, OpVT, in tryShiftAmountMod()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2521 EVT OpVT = Op.getOperand(0).getValueType(); in LowerSINT_TO_FP() local
2522 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2524 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2528 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { in LowerSINT_TO_FP()
2529 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2536 if (!TLI.isTypeLegal(OpVT)) in LowerSINT_TO_FP()
2541 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2568 EVT OpVT = Op.getOperand(0).getValueType(); in LowerUINT_TO_FP() local
2569 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2573 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1804 EVT OpVT = Ops[0].getValueType(); in PerformDAGCombine() local
1805 if (InVal.getValueType() != OpVT) in PerformDAGCombine()
1806 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
1807 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1808 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8061 MVT OpVT = Op.getOperand(0).getSimpleValueType(); in LowerOperation() local
8062 if (OpVT.isScalarInteger()) { in LowerOperation()
8086 DL, VT, LHS, DAG.getSignedConstant(Imm + 1, DL, OpVT), CCVal); in LowerOperation()
10315 MVT OpVT = ScalarOp.getSimpleValueType(); in lowerVectorIntrinsicScalars() local
10319 if (!OpVT.isScalarInteger() || OpVT == XLenVT) in lowerVectorIntrinsicScalars()
10323 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicScalars()
10344 assert(XLenVT == MVT::i32 && OpVT == MVT::i64 && in lowerVectorIntrinsicScalars()
10508 MVT OpVT = Op0.getSimpleValueType(); in lowerCttzElts() local
10509 MVT ContainerVT = OpVT; in lowerCttzElts()
10510 if (OpVT.isFixedLengthVector()) { in lowerCttzElts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp865 MVT OpVT = Op.getSimpleValueType(); in lowerSCALAR_TO_VECTOR() local
867 SDValue Vector = DAG.getUNDEF(OpVT); in lowerSCALAR_TO_VECTOR()
871 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, OpVT, Vector, Val, Idx); in lowerSCALAR_TO_VECTOR()
2749 EVT OpVT = Op0.getValueType(); in lowerUINT_TO_FP() local
2751 RTLIB::Libcall LC = RTLIB::getUINTTOFP(OpVT, RetVT); in lowerUINT_TO_FP()
2753 CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true); in lowerUINT_TO_FP()
2774 EVT OpVT = Op0.getValueType(); in lowerSINT_TO_FP() local
2776 RTLIB::Libcall LC = RTLIB::getSINTTOFP(OpVT, RetVT); in lowerSINT_TO_FP()
2778 CallOptions.setTypeListBeforeSoften(OpVT, RetVT, true); in lowerSINT_TO_FP()
4073 EVT OpVT = Src.getValueType(); in ReplaceNodeResults() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1303 EVT OpVT = OpI1.getValueType(); in ppHoistZextI1() local
1304 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) in ppHoistZextI1()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp7579 EVT OpVT = Op.getValueType(); in combineExtract() local
7580 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize(); in combineExtract()
7609 EVT OpVT = Op.getOperand(0).getValueType(); in combineExtract() local
7611 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize(); in combineExtract()
11037 EVT OpVT = Op.getValueType(); in lowerVECREDUCE_ADD() local
11039 assert(OpVT.isVector() && "Operand type for VECREDUCE_ADD is not a vector."); in lowerVECREDUCE_ADD()
11044 SDValue Zero = DAG.getSplatBuildVector(OpVT, DL, DAG.getConstant(0, DL, VT)); in lowerVECREDUCE_ADD()
11047 switch (OpVT.getScalarSizeInBits()) { in lowerVECREDUCE_ADD()
11064 ISD::EXTRACT_VECTOR_ELT, DL, VT, DAG.getBitcast(OpVT, Op), in lowerVECREDUCE_ADD()
11065 DAG.getConstant(OpVT.getVectorNumElements() - 1, DL, MVT::i32)); in lowerVECREDUCE_ADD()

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