/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsRegisterBankInfo.h | 76 bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_64() 77 if (InstTy == InstType::Ambiguous && OpSize == 64) in isAmbiguous_64() 82 bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32() 83 if (InstTy == InstType::Ambiguous && OpSize == 32) in isAmbiguous_32() 88 bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { in isAmbiguous_32or64() 89 if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64)) in isAmbiguous_32or64() 95 unsigned OpSize) const { in isAmbiguousWithMergeOrUnmerge_64() 96 if (InstTy == InstType::AmbiguousWithMergeOrUnmerge && OpSize == 64) in isAmbiguousWithMergeOrUnmerge_64() 101 bool isFloatingPoint_32or64(InstType InstTy, unsigned OpSize) cons in isFloatingPoint_32or64() 75 isAmbiguous_64(InstType InstTy,unsigned OpSize) isAmbiguous_64() argument 81 isAmbiguous_32(InstType InstTy,unsigned OpSize) isAmbiguous_32() argument 87 isAmbiguous_32or64(InstType InstTy,unsigned OpSize) isAmbiguous_32or64() argument 94 isAmbiguousWithMergeOrUnmerge_64(InstType InstTy,unsigned OpSize) isAmbiguousWithMergeOrUnmerge_64() argument 100 isFloatingPoint_32or64(InstType InstTy,unsigned OpSize) isFloatingPoint_32or64() argument 106 isFloatingPoint_64(InstType InstTy,unsigned OpSize) isFloatingPoint_64() argument 112 isInteger_32(InstType InstTy,unsigned OpSize) isInteger_32() argument [all...] |
/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.h | 196 uint8_t OpSize; member 283 uint8_t OpSize); 294 uint8_t OpSize); 299 uint8_t OpSize); 304 uint8_t OpSize); 306 uint8_t OpSize); 308 uint8_t OpSize); 310 uint8_t OpSize); 312 uint8_t OpSize); 314 writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize); [all …]
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H A D | X86RecognizableInstr.cpp | 119 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstrBase() 338 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext() 342 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext() 344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext() 348 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext() 350 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext() 369 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext() 371 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext() 379 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext() 381 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext() [all …]
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H A D | X86FoldTablesEmitter.cpp | 373 RegRI.OpSize, RegRI.AdSize, RegRI.HasREX_W, RegRI.HasVEX_4V, in operator ()() 380 MemRI.OpSize, MemRI.AdSize, MemRI.HasREX_W, MemRI.HasVEX_4V, in operator ()()
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/freebsd/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
H A D | MCExternalSymbolizer.cpp | 36 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand() argument 42 !GetOpInfo(DisInfo, Address, Offset, OpSize, InstSize, 1, &SymbolicOp)) { in tryAddingSymbolicOperand() 55 if (!SymbolLookUp || (OpSize == 1 && !IsBranch)) in tryAddingSymbolicOperand()
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H A D | MCDisassembler.cpp | 30 uint64_t Offset, uint64_t OpSize, in tryAddingSymbolicOperand() argument 35 OpSize, InstSize); in tryAddingSymbolicOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMLegalizerInfo.cpp | 377 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local 382 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); in legalizeCustom() 394 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); in legalizeCustom() 395 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); in legalizeCustom()
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H A D | ARMInstructionSelector.cpp | 462 unsigned OpRegBank, unsigned OpSize) in CmpConstants() 465 OperandSize(OpSize) {} in CmpConstants()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64ExternalSymbolizer.h | 32 uint64_t Offset, uint64_t OpSize,
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H A D | AArch64ExternalSymbolizer.cpp | 63 bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) { in tryAddingSymbolicOperand() argument 76 if (!GetOpInfo || !GetOpInfo(DisInfo, Address, /*Offset=*/0, OpSize, InstSize, in tryAddingSymbolicOperand()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/MCDisassembler/ |
H A D | MCExternalSymbolizer.h | 49 uint64_t Offset, uint64_t OpSize,
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H A D | MCSymbolizer.h | 72 uint64_t OpSize, uint64_t InstSize) = 0;
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H A D | MCDisassembler.h | 206 bool IsBranch, uint64_t Offset, uint64_t OpSize,
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/freebsd/contrib/llvm-project/llvm/include/llvm-c/ |
H A D | DisassemblerTypes.h | 49 uint64_t OpSize, uint64_t InstSize,
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | LowerMemIntrinsics.cpp | 161 Value *Len, Value *OpSize, in getRuntimeLoopCount() argument 166 return B.CreateUDiv(Len, OpSize); in getRuntimeLoopCount() 171 Value *Len, Value *OpSize, in getRuntimeLoopRemainder() argument 176 return B.CreateURem(Len, OpSize); in getRuntimeLoopRemainder()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64RegisterBankInfo.cpp | 755 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local 765 OpSize[Idx] = Ty.getSizeInBits().getKnownMinValue(); in getInstrMapping() 841 TypeSize::getFixed(OpSize[0])); in getInstrMapping() 1134 getValueMapping(OpRegBankIdx[Idx], TypeSize::getFixed(OpSize[Idx])); in getInstrMapping()
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H A D | AArch64InstructionSelector.cpp | 814 unsigned OpSize) { in selectBinaryOp() argument 817 if (OpSize == 32) { in selectBinaryOp() 828 } else if (OpSize == 64) { in selectBinaryOp() 844 switch (OpSize) { in selectBinaryOp() 885 unsigned OpSize) { in selectLoadStoreUIOp() argument 889 switch (OpSize) { in selectLoadStoreUIOp() 901 switch (OpSize) { in selectLoadStoreUIOp() 3096 const unsigned OpSize = Ty.getSizeInBits(); in select() local 3101 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize); in select() 4450 unsigned OpSize = Ty.getSizeInBits(); in emitFPCompare() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
H A D | PPCInstructionSelector.cpp | 155 unsigned OpSize) { in selectLoadStoreOp() argument 159 switch (OpSize) { in selectLoadStoreOp() 169 switch (OpSize) { in selectLoadStoreOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.h | 311 uint64_t Offset, uint64_t OpSize,
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrFormats.td | 232 OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change 234 bits<2> OpSizeBits = OpSize.Value;
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | GISelKnownBits.cpp | 497 unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); in computeKnownBitsImpl() local 503 Known.insertBits(SrcOpKnown, I * OpSize); in computeKnownBitsImpl()
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/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/ |
H A D | DWARFEmitter.cpp | 1025 if (Expected<uint64_t> OpSize = in writeListEntry() local 1027 DescriptionsLength += *OpSize; in writeListEntry() 1029 return OpSize.takeError(); in writeListEntry()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 658 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local 663 OpSize = SubRegSize / 8; in foldMemoryOperand() 666 MemSize = std::max(MemSize, OpSize); in foldMemoryOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 894 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local 895 bool Is64 = OpSize % 64 == 0; in executeInWaterfallLoop() 898 unsigned NumParts = OpSize / PartSize; in executeInWaterfallLoop() 4625 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local 4626 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping() 4627 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping() 4830 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local 4833 OpdsMapping[2] = AMDGPU::getValueMapping(regBankID, OpSize); in getInstrMapping()
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/freebsd/contrib/llvm-project/llvm/tools/llvm-objdump/ |
H A D | MachODump.cpp | 2807 uint64_t OpSize, uint64_t InstSize, int TagType, in SymbolizerGetOpInfo() argument 2825 if (OpSize != 1 && OpSize != 2 && OpSize != 4 && OpSize != 0) in SymbolizerGetOpInfo() 2905 if (OpSize != 1 && OpSize != 2 && OpSize != 4 && OpSize != 0) in SymbolizerGetOpInfo()
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