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Searched refs:OpReg (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineConvergenceVerifier.cpp56 Register OpReg = MO.getReg(); in findAndCheckConvergenceTokenUsed() local
57 if (!OpReg.isVirtual()) in findAndCheckConvergenceTokenUsed()
60 const MachineInstr *Def = MRI.getUniqueVRegDef(OpReg); in findAndCheckConvergenceTokenUsed()
69 {Context.print(OpReg), Context.print(&MI)}); in findAndCheckConvergenceTokenUsed()
73 {Context.print(OpReg), Context.print(&MI)}); in findAndCheckConvergenceTokenUsed()
H A DMachineInstr.cpp2183 Register OpReg = MO.getReg(); in clearRegisterKills() local
2184 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp138 inline Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg) { in getTypeReg() argument
139 SPIRVType *TypeInst = MRI->getVRegDef(OpReg); in getTypeReg()
142 : OpReg; in getTypeReg()
147 Register OpReg, unsigned OpIdx, in doInsertBitcast() argument
154 .addUse(OpReg) in doInsertBitcast()
184 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrTypes() local
185 Register OpTypeReg = getTypeReg(MRI, OpReg); in validatePtrTypes()
207 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validatePtrTypes()
218 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupWaitEventsPtr() local
219 Register OpTypeReg = getTypeReg(MRI, OpReg); in validateGroupWaitEventsPtr()
[all …]
H A DSPIRVPreLegalizer.cpp176 Register ResVReg, Register OpReg) { in buildOpBitcast() argument
178 SPIRVType *OpType = GR->getSPIRVTypeForVReg(OpReg); in buildOpBitcast()
186 MIB.buildInstr(TargetOpcode::COPY).addDef(ResVReg).addUse(OpReg); in buildOpBitcast()
191 .addUse(OpReg); in buildOpBitcast()
478 Register OpReg = Op.getReg(); in processInstr() local
479 SPIRVType *SpvType = GR->getSPIRVTypeForVReg(OpReg); in processInstr()
482 GR->assignSPIRVTypeToVReg(KnownResType, OpReg, *MI.getMF()); in processInstr()
485 if (!MRI.getRegClassOrNull(OpReg)) in processInstr()
486 MRI.setRegClass(OpReg, GR->getRegClass(SpvType)); in processInstr()
487 if (!MRI.getType(OpReg).isValid()) in processInstr()
[all …]
H A DSPIRVInstructionSelector.cpp469 static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) { in isConstReg() argument
471 if (MachineInstr *OpDef = MRI->getVRegDef(OpReg)) in isConstReg()
1084 Register OpReg = I.getOperand(1).getReg(); in selectBitcast() local
1085 SPIRVType *OpType = OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr; in selectBitcast()
2325 Register OpReg = I.getOperand(1).getReg(); in selectFreeze() local
2326 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) { in selectFreeze()
2347 Reg = OpReg; in selectFreeze()
2408 Register OpReg = I.getOperand(OpIdx).getReg(); in selectSplatVector() local
2409 bool IsConst = isConstReg(MRI, OpReg); in selectSplatVector()
2422 MIB.addUse(OpReg); in selectSplatVector()
[all …]
H A DSPIRVModuleAnalysis.h245 void visitFunPtrUse(Register OpReg, InstrGRegsMap &SignatureToGReg,
H A DSPIRVModuleAnalysis.cpp323 Register OpReg, InstrGRegsMap &SignatureToGReg, in visitFunPtrUse() argument
344 MAI.setRegisterAlias(MF, OpReg, GlobalFunDefReg); in visitFunPtrUse()
359 Register OpReg = MO.getReg(); in visitDecl() local
362 MRI.getRegClass(OpReg) == &SPIRV::pIDRegClass) { in visitDecl()
363 visitFunPtrUse(OpReg, SignatureToGReg, GlobalToGReg, MF, MI); in visitDecl()
370 if (const MachineInstr *OpDefMI = MRI.getUniqueVRegDef(OpReg)) { in visitDecl()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp192 const MCAOperand *OpReg = Inst.getOperand(0); in computeWaitCnt() local
194 assert(OpReg && OpReg->isReg() && "First operand should be a register."); in computeWaitCnt()
196 if (OpReg->getReg() != AMDGPU::SGPR_NULL) { in computeWaitCnt()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1734 Register OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1735 if (!OpReg) in X86SelectBranch()
1739 .addReg(OpReg).addImm(1); in X86SelectBranch()
1770 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1771 if (!OpReg) in X86SelectBranch()
1775 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1776 Register KOpReg = OpReg; in X86SelectBranch()
1777 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1779 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1781 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); in X86SelectBranch()
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H A DX86SpeculativeLoadHardening.cpp1649 Register OpReg = Op->getReg(); in hardenLoadAddr() local
1650 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1688 .addReg(OpReg); in hardenLoadAddr()
1719 .addReg(OpReg); in hardenLoadAddr()
1732 .addReg(OpReg); in hardenLoadAddr()
1741 .addReg(OpReg) in hardenLoadAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp298 Register OpReg = MO.getReg(); in optimizeSDPattern() local
300 if (!OpReg.isVirtual()) in optimizeSDPattern()
303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
H A DARMInstructionSelector.cpp1054 Register OpReg = I.getOperand(2).getReg(); in select() local
1055 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
H A DARMFastISel.cpp1305 Register OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1306 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1309 .addReg(OpReg).addImm(1)); in SelectBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp3047 Register OpReg = Op.getReg(); in fixVALUMaskWriteHazard() local
3052 if (OpReg == AMDGPU::EXEC || in fixVALUMaskWriteHazard()
3053 OpReg == AMDGPU::EXEC_LO || in fixVALUMaskWriteHazard()
3054 OpReg == AMDGPU::EXEC_HI) in fixVALUMaskWriteHazard()
3058 if (OpReg == AMDGPU::VCC || in fixVALUMaskWriteHazard()
3059 OpReg == AMDGPU::VCC_LO || in fixVALUMaskWriteHazard()
3060 OpReg == AMDGPU::VCC_HI) in fixVALUMaskWriteHazard()
3064 if (TRI.isSGPRReg(MRI, OpReg)) in fixVALUMaskWriteHazard()
H A DAMDGPURegisterBankInfo.cpp879 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
880 LLT OpTy = MRI.getType(OpReg); in executeInWaterfallLoop()
882 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
887 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
891 Register CurrentLaneReg = buildReadFirstLane(B, MRI, OpReg); in executeInWaterfallLoop()
903 OpParts.push_back(OpReg); in executeInWaterfallLoop()
906 auto UnmergeOp = B.buildUnmerge(PartTy, OpReg); in executeInWaterfallLoop()
3675 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
3677 if (!OpReg) in getImageMapping()
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H A DAMDGPUInstructionSelector.cpp2836 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2847 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg) in selectG_FNEG()
2854 .addReg(OpReg) in selectG_FNEG()
2874 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2889 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg) in selectG_FABS()
2896 .addReg(OpReg) in selectG_FABS()
H A DSIInstrInfo.cpp6528 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
6532 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
6540 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).addReg(OpReg); in legalizeGenericOperand()
6543 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
6549 foldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1666 Register OpReg = getRegForValue(In); in selectFNeg() local
1667 if (!OpReg) in selectFNeg()
1673 OpReg); in selectFNeg()
1688 ISD::BITCAST, OpReg); in selectFNeg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4554 MCRegister OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4571 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4691 MCRegister OpReg = Inst.getOperand(2).getReg(); in expandSle() local
4708 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
5381 MCRegister OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5385 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5386 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5391 MCRegister Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5462 MCRegister OpReg = Inst.getOperand(2).getReg(); in expandSne() local
5466 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6735 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
6737 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
6744 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarExtract()
6799 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
6801 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
6805 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
6808 DstRegs.push_back(OpReg); in narrowScalarInsert()
6840 Register SegReg = OpReg; in narrowScalarInsert()
6844 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
9495 Register OpReg = MI.getOperand(1).getReg(); in lowerAbsToAddXor() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp272 MCRegister OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
273 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5949 Register OpReg = I.getOperand(i).getReg(); in selectBuildVector() local
5951 if (!getOpcodeDef<GImplicitDef>(OpReg, MRI)) { in selectBuildVector()
5952 PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB); in selectBuildVector()
8061 Register OpReg = MO.getReg(); in fixupPHIOpBanks() local
8062 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg); in fixupPHIOpBanks()
8065 auto *OpDef = MRI.getVRegDef(OpReg); in fixupPHIOpBanks()
8066 const LLT &Ty = MRI.getType(OpReg); in fixupPHIOpBanks()
8075 auto Copy = MIB.buildCopy(Ty, OpReg); in fixupPHIOpBanks()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7499 MCRegister OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7500 if (OpReg == Reg) in checkLowRegisterList()
7503 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
7513 MCRegister OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
7514 if (OpReg == Reg) in listContainsReg()