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Searched refs:OpReg (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineConvergenceVerifier.cpp57 Register OpReg = MO.getReg(); in findAndCheckConvergenceTokenUsed() local
58 if (!OpReg.isVirtual()) in findAndCheckConvergenceTokenUsed()
61 const MachineInstr *Def = MRI.getUniqueVRegDef(OpReg); in findAndCheckConvergenceTokenUsed()
70 {Context.print(OpReg), Context.print(&MI)}); in findAndCheckConvergenceTokenUsed()
74 {Context.print(OpReg), Context.print(&MI)}); in findAndCheckConvergenceTokenUsed()
H A DMachineInstr.cpp2069 Register OpReg = MO.getReg(); in clearRegisterKills() local
2070 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp107 inline Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg) { in getTypeReg() argument
108 SPIRVType *TypeInst = MRI->getVRegDef(OpReg); in getTypeReg()
111 : OpReg; in getTypeReg()
116 Register OpReg, unsigned OpIdx, in doInsertBitcast() argument
123 .addUse(OpReg) in doInsertBitcast()
156 Register OpReg = I.getOperand(OpIdx).getReg(); in validatePtrTypes() local
157 Register OpTypeReg = getTypeReg(MRI, OpReg); in validatePtrTypes()
179 doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType); in validatePtrTypes()
190 Register OpReg = I.getOperand(OpIdx).getReg(); in validateGroupWaitEventsPtr() local
191 Register OpTypeReg = getTypeReg(MRI, OpReg); in validateGroupWaitEventsPtr()
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H A DSPIRVInstructionSelector.cpp713 Register OpReg = I.getOperand(1).getReg(); in selectBitcast() local
714 SPIRVType *OpType = OpReg.isValid() ? GR.getSPIRVTypeForVReg(OpReg) : nullptr; in selectBitcast()
1371 Register OpReg = I.getOperand(1).getReg(); in selectFreeze() local
1372 if (MachineInstr *Def = MRI->getVRegDef(OpReg)) { in selectFreeze()
1391 Reg = OpReg; in selectFreeze()
1432 Register OpReg = ResType->getOperand(2).getReg(); in getArrayComponentCount() local
1433 SPIRVType *OpDef = MRI->getVRegDef(OpReg); in getArrayComponentCount()
1488 static bool isConstReg(MachineRegisterInfo *MRI, Register OpReg) { in isConstReg() argument
1490 if (SPIRVType *OpDef = MRI->getVRegDef(OpReg)) in isConstReg()
1511 Register OpReg = I.getOperand(OpIdx).getReg(); in selectSplatVector() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp191 const MCAOperand *OpReg = Inst.getOperand(0); in computeWaitCnt() local
193 assert(OpReg && OpReg->isReg() && "First operand should be a register."); in computeWaitCnt()
195 if (OpReg->getReg() != AMDGPU::SGPR_NULL) { in computeWaitCnt()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1733 Register OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1734 if (OpReg == 0) return false; in X86SelectBranch()
1737 .addReg(OpReg).addImm(1); in X86SelectBranch()
1768 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1769 if (OpReg == 0) return false; in X86SelectBranch()
1772 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1773 unsigned KOpReg = OpReg; in X86SelectBranch()
1774 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1776 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1778 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); in X86SelectBranch()
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H A DX86SpeculativeLoadHardening.cpp1652 Register OpReg = Op->getReg(); in hardenLoadAddr() local
1653 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1691 .addReg(OpReg); in hardenLoadAddr()
1722 .addReg(OpReg); in hardenLoadAddr()
1735 .addReg(OpReg); in hardenLoadAddr()
1744 .addReg(OpReg) in hardenLoadAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp297 Register OpReg = MO.getReg(); in optimizeSDPattern() local
299 if (!OpReg.isVirtual()) in optimizeSDPattern()
302 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
H A DARMInstructionSelector.cpp1054 Register OpReg = I.getOperand(2).getReg(); in select() local
1055 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
H A DARMFastISel.cpp1263 Register OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1267 .addReg(OpReg).addImm(1)); in SelectBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp2844 Register OpReg = Op.getReg(); in fixVALUMaskWriteHazard() local
2849 if (OpReg == AMDGPU::EXEC || in fixVALUMaskWriteHazard()
2850 OpReg == AMDGPU::EXEC_LO || in fixVALUMaskWriteHazard()
2851 OpReg == AMDGPU::EXEC_HI) in fixVALUMaskWriteHazard()
2855 if (OpReg == AMDGPU::VCC || in fixVALUMaskWriteHazard()
2856 OpReg == AMDGPU::VCC_LO || in fixVALUMaskWriteHazard()
2857 OpReg == AMDGPU::VCC_HI) in fixVALUMaskWriteHazard()
2861 if (TRI.isSGPRReg(MRI, OpReg)) in fixVALUMaskWriteHazard()
H A DAMDGPURegisterBankInfo.cpp879 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
880 LLT OpTy = MRI.getType(OpReg); in executeInWaterfallLoop()
882 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
886 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
887 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
891 Register CurrentLaneReg = buildReadFirstLane(B, MRI, OpReg); in executeInWaterfallLoop()
903 OpParts.push_back(OpReg); in executeInWaterfallLoop()
906 auto UnmergeOp = B.buildUnmerge(PartTy, OpReg); in executeInWaterfallLoop()
3599 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
3601 if (!OpReg) in getImageMapping()
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H A DAMDGPUInstructionSelector.cpp2641 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2652 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg) in selectG_FNEG()
2659 .addReg(OpReg) in selectG_FNEG()
2679 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2694 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg) in selectG_FABS()
2701 .addReg(OpReg) in selectG_FABS()
H A DSIInstrInfo.cpp6223 Register OpReg = Op.getReg(); in legalizeGenericOperand() local
6227 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
6239 MachineInstr *Def = MRI.getVRegDef(OpReg); in legalizeGenericOperand()
6245 foldImmediate(*Copy, *Def, OpReg, &MRI); in legalizeGenericOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1725 Register OpReg = getRegForValue(In); in selectFNeg() local
1726 if (!OpReg) in selectFNeg()
1732 OpReg); in selectFNeg()
1747 ISD::BITCAST, OpReg); in selectFNeg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4611 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4628 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4748 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
4765 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
5439 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5443 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5449 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5520 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
5524 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6043 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
6045 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
6052 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarExtract()
6109 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
6111 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
6115 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
6118 DstRegs.push_back(OpReg); in narrowScalarInsert()
6150 Register SegReg = OpReg; in narrowScalarInsert()
6154 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
8549 Register OpReg = MI.getOperand(1).getReg(); in lowerAbsToAddXor() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
242 return getVectorRegSize(OpReg) / ScalarSize; in getRegOperandNumElts()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp5789 Register OpReg = I.getOperand(i).getReg(); in selectBuildVector() local
5791 if (!getOpcodeDef<GImplicitDef>(OpReg, MRI)) { in selectBuildVector()
5792 PrevMI = &*emitLaneInsert(std::nullopt, DstVec, OpReg, i - 1, RB, MIB); in selectBuildVector()
7883 Register OpReg = MO.getReg(); in fixupPHIOpBanks() local
7884 const RegisterBank *RB = MRI.getRegBankOrNull(OpReg); in fixupPHIOpBanks()
7887 auto *OpDef = MRI.getVRegDef(OpReg); in fixupPHIOpBanks()
7888 const LLT &Ty = MRI.getType(OpReg); in fixupPHIOpBanks()
7897 auto Copy = MIB.buildCopy(Ty, OpReg); in fixupPHIOpBanks()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7467 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList() local
7468 if (OpReg == Reg) in checkLowRegisterList()
7471 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
7481 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg() local
7482 if (OpReg == Reg) in listContainsReg()