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Searched refs:OpNode (Results 1 – 25 of 47) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td181 multiclass Binary_rv<SDPatternOperator OpNode,
186 (OpNode
202 def : Pat<(OpNode
209 def : Pat<(OpNode
217 multiclass Binary_vr<SDPatternOperator OpNode,
222 (OpNode
238 def : Pat<(OpNode
245 def : Pat<(OpNode
253 multiclass Binary_vv<SDPatternOperator OpNode,
258 (OpNode
[all …]
H A DVEInstrInfo.td545 SDPatternOperator OpNode = null_frag,
550 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
551 // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
556 [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi immOp:$sy)))]>;
560 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
564 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), (Tyi mOp:$sz)))]> {
577 SDPatternOperator OpNode = null_frag,
581 [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>;
585 [(set Tyo:$sx, (OpNode (Tyi immOp:$sy), Tyi:$sz))]>;
589 [(set Tyo:$sx, (OpNode Tyi:$sy, (Tyi mOp:$sz)))]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX10.td59 multiclass avx10_minmax_packed_base<string OpStr, X86VectorVTInfo VTI, SDNode OpNode> {
64 (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
70 (VTI.VT (OpNode VTI.RC:$src1, (VTI.LdFrag addr:$src2),
78 (VTI.VT (OpNode VTI.RC:$src1, (VTI.BroadcastLdFrag addr:$src2),
85 multiclass avx10_minmax_packed_sae<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {
90 (VTI.info512.VT (OpNode (VTI.info512.VT VTI.info512.RC:$src1),
96 multiclass avx10_minmax_packed<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {
98 defm Z : avx10_minmax_packed_base<OpStr, VTI.info512, OpNode>, EVEX_V512;
100 defm Z256 : avx10_minmax_packed_base<OpStr, VTI.info256, OpNode>, EVEX_V256;
101 defm Z128 : avx10_minmax_packed_base<OpStr, VTI.info128, OpNode>, EVEX_V128;
[all …]
H A DX86InstrAVX512.td1187 X86VectorVTInfo _, SDPatternOperator OpNode,
1194 (_.VT (OpNode SrcRC:$src)), /*IsCommutable*/0,
1200 X86VectorVTInfo _, SDPatternOperator OpNode,
1210 def : Pat <(_.VT (OpNode SrcRC:$src)),
1215 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1219 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1225 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1229 OpNode, SrcRC, Subreg>, EVEX_V512;
1232 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1234 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
[all …]
H A DX86InstrFMA.td179 SDPatternOperator OpNode,
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
200 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
220 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
236 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
244 SDPatternOperator OpNode, RegisterClass RC,
247 x86memop, RC, OpNode, sched>;
249 x86memop, RC, OpNode, sched>;
[all …]
H A DX86InstrFPStack.td76 multiclass FPBinary_rr<SDPatternOperator OpNode> {
80 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
82 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
84 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
89 multiclass FPBinary<SDPatternOperator OpNode, Format fp, string asmstring,
96 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
98 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
103 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
105 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
110 (OpNode RFP6
[all...]
H A DX86InstrXOP.td94 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
106 (vt128 (OpNode (vt128 VR128:$src1),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
140 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
244 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128,
253 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
261 (vt128 (OpNode (vt12
[all...]
H A DX86InstrSSE.td20 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
44 SDPatternOperator OpNode, RegisterClass RC,
53 [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>,
60 [(set RC:$dst, (VT (OpNode RC:$src1, (mem_frags addr:$src2))))], d>,
66 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
76 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>,
83 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
194 multiclass sse12_move_rr<SDNode OpNode, ValueType vt, string base_opc,
[all …]
H A DX86InstrTBM.td20 SDNode OpNode, Operand immtype,
26 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>,
32 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td2478 SDPatternOperator OpNode>
2481 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2623 SDNode OpNode>
2625 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
2628 SDNode OpNode>
2630 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]> {
2635 SDNode OpNode, SDNode OpNode_setflags> {
2636 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2640 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2659 string asm, SDPatternOperator OpNode,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
[all …]
H A DMipsInstrFPU.td112 SDPatternOperator OpNode= null_frag> :
115 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
121 SDPatternOperator OpNode = null_frag> {
122 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
123 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
129 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
137 SDPatternOperator OpNode = null_frag> :
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
146 SDPatternOperator OpNode= null_frag> {
[all …]
H A DMipsMSAInstrInfo.td1048 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1055 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1059 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1066 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1070 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1077 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1081 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1088 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1092 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1099 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[all …]
H A DMicroMipsInstrFPU.td14 SDPatternOperator OpNode = null_frag> {
15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
H A DMicroMipsDSPInstrInfo.td179 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
215 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
252 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
325 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
330 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
H A DMipsInstrInfo.td1332 SDPatternOperator OpNode = null_frag>:
1335 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1345 SDPatternOperator OpNode = null_frag> :
1348 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1374 SDPatternOperator OpNode = null_frag,
1378 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1383 SDPatternOperator OpNode = null_frag>:
1386 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1399 SDPatternOperator OpNode = null_frag,
1403 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZalasr.td65 class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
66 : Pat<(vt (OpNode (vt GPRMemZeroOffset:$rs1))), (Inst GPRMemZeroOffset:$rs1)>;
71 class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
72 : Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)),
H A DRISCVInstrInfoF.td531 class PatSetCC<DAGOperand Ty, SDPatternOperator OpNode, CondCode Cond,
533 : Pat<(XLenVT (OpNode (vt Ty:$rs1), Ty:$rs2, Cond)), (Inst $rs1, $rs2)>;
534 multiclass PatSetCC_m<SDPatternOperator OpNode, CondCode Cond,
537 def Ext.Suffix : PatSetCC<Ext.PrimaryTy, OpNode, Cond,
541 class PatFprFpr<SDPatternOperator OpNode, RVInstR Inst,
543 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2)>;
544 multiclass PatFprFpr_m<SDPatternOperator OpNode, RVInstR Inst,
547 def Ext.Suffix : PatFprFpr<OpNode, !cast<RVInstR>(Inst#Ext.Suffix),
551 class PatFprFprDynFrm<SDPatternOperator OpNode, RVInstRFrm Inst,
553 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2, FRM_DYN)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td311 multiclass ALU<BPFArithOp Opc, int off, string OpcodeStr, SDNode OpNode> {
316 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
321 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
326 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
331 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
516 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
517 : STORE<Opc, OpcodeStr, [(OpNode GPR:$src, ADDRri:$addr)]>;
627 class LOADi64<BPFWidthModifer SizeOp, BPFModeModifer ModOp, string OpcodeStr, PatFrag OpNode>
628 : LOAD<SizeOp, ModOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
1066 class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td89 class VecCond<SDPatternOperator OpNode, ValueType TyNode,
92 [(set GPR:$rd, (OpNode (TyNode RC:$vj)))]> {
1287 multiclass PatVr<SDPatternOperator OpNode, string Inst> {
1288 def : Pat<(v16i8 (OpNode (v16i8 LSX128:$vj))),
1290 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))),
1292 def : Pat<(v4i32 (OpNode (v4i32 LSX128:$vj))),
1294 def : Pat<(v2i64 (OpNode (v2i64 LSX128:$vj))),
1298 multiclass PatVrF<SDPatternOperator OpNode, string Inst> {
1299 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))),
1301 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))),
[all …]
H A DLoongArchLASXInstrInfo.td1105 multiclass PatXr<SDPatternOperator OpNode, string Inst> {
1106 def : Pat<(v32i8 (OpNode (v32i8 LASX256:$xj))),
1108 def : Pat<(v16i16 (OpNode (v16i16 LASX256:$xj))),
1110 def : Pat<(v8i32 (OpNode (v8i32 LASX256:$xj))),
1112 def : Pat<(v4i64 (OpNode (v4i64 LASX256:$xj))),
1116 multiclass PatXrF<SDPatternOperator OpNode, string Inst> {
1117 def : Pat<(v8f32 (OpNode (v8f32 LASX256:$xj))),
1119 def : Pat<(v4f64 (OpNode (v4f64 LASX256:$xj))),
1123 multiclass PatXrXr<SDPatternOperator OpNode, string Inst> {
1124 def : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 LASX256:$xk)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td288 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
296 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
299 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
303 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
309 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
480 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
483 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
496 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
499 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2523 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2526 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2529 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2532 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2588 ValueType TyD, ValueType TyQ, SDNode OpNode>
2591 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2606 ValueType TyQ, ValueType TyD, SDNode OpNode>
2609 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2635 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2639 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td284 class I16x2<string OpcStr, SDNode OpNode> :
287 [(set v2i16:$dst, (OpNode v2i16:$a, v2i16:$b))]>,
304 multiclass FMINIMUMMAXIMUM<string OpcStr, bit NaN, SDNode OpNode> {
311 [(set f64:$dst, (OpNode f64:$a, f64:$b))]>;
316 [(set f64:$dst, (OpNode f64:$a, fpimm:$b))]>;
323 [(set f32:$dst, (OpNode f32:$a, f32:$b))]>;
329 [(set f32:$dst, (OpNode f32:$a, fpimm:$b))]>;
336 [(set f16:$dst, (OpNode f16:$a, f16:$b))]>,
344 [(set v2f16:$dst, (OpNode v2f16:$a, v2f16:$b))]>,
350 [(set bf16:$dst, (OpNode bf16:$a, bf16:$b))]>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td243 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
246 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
249 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
260 SDNode OpNode> {
263 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
266 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
269 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
272 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
281 SDNode OpNode> {
284 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]

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