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Searched refs:OpNo (Results 1 – 25 of 179) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.h44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
46 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
48 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
52 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem() argument
54 printMemReference(MI, OpNo, O); in printbytemem()
56 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem() argument
58 printMemReference(MI, OpNo, O); in printwordmem()
60 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem() argument
[all …]
H A DX86ATTInstPrinter.h43 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
45 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
49 void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
51 void printbytemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printbytemem() argument
52 printMemReference(MI, OpNo, O); in printbytemem()
54 void printwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printwordmem() argument
55 printMemReference(MI, OpNo, O); in printwordmem()
57 void printdwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printdwordmem() argument
58 printMemReference(MI, OpNo, O); in printdwordmem()
60 void printqwordmem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printqwordmem() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h39 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
41 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
43 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
46 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
48 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
50 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
52 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
[all …]
H A DR600InstPrinter.cpp28 void R600InstPrinter::printAbs(const MCInst *MI, unsigned OpNo, in printAbs() argument
30 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, '|'); in printAbs()
33 void R600InstPrinter::printBankSwizzle(const MCInst *MI, unsigned OpNo, in printBankSwizzle() argument
35 int BankSwizzle = MI->getOperand(OpNo).getImm(); in printBankSwizzle()
57 void R600InstPrinter::printClamp(const MCInst *MI, unsigned OpNo, in printClamp() argument
59 AMDGPUInstPrinter::printIfSet(MI, OpNo, O, "_SAT"); in printClamp()
62 void R600InstPrinter::printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printCT() argument
63 unsigned CT = MI->getOperand(OpNo).getImm(); in printCT()
76 void R600InstPrinter::printKCache(const MCInst *MI, unsigned OpNo, in printKCache() argument
78 int KCacheMode = MI->getOperand(OpNo).getImm(); in printKCache()
[all …]
H A DAMDGPUInstPrinter.cpp50 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo, in printU4ImmOperand() argument
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
56 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument
59 const MCOperand &Op = MI->getOperand(OpNo); in printU16ImmOperand()
71 printU32ImmOperand(MI, OpNo, STI, O); in printU16ImmOperand()
74 void AMDGPUInstPrinter::printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU4ImmDecOperand() argument
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
79 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU8ImmDecOperand() argument
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
84 void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU16ImmDecOperand() argument
[all …]
H A DR600InstPrinter.h28 void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);
29 void printBankSwizzle(const MCInst *MI, unsigned OpNo, raw_ostream &O);
30 void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O);
31 void printCT(const MCInst *MI, unsigned OpNo, raw_ostream &O);
32 void printKCache(const MCInst *MI, unsigned OpNo, raw_ostream &O);
33 void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O);
34 void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O);
35 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printOMOD(const MCInst *MI, unsigned OpNo, raw_ostream &O);
[all …]
H A DAMDGPUMCCodeEmitter.cpp52 void getMachineOpValueT16(const MCInst &MI, unsigned OpNo, APInt &Op,
56 void getMachineOpValueT16Lo128(const MCInst &MI, unsigned OpNo, APInt &Op,
62 void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
66 void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
70 void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
74 void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
78 void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
85 unsigned OpNo, APInt &Op,
456 void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, in getSOPPBrEncoding() argument
460 const MCOperand &MO = MI.getOperand(OpNo); in getSOPPBrEncoding()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.h60 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
67 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
73 unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
77 unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
81 unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
87 unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
94 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
101 unsigned getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
108 unsigned getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
115 unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
[all...]
H A DMipsMCCodeEmitter.cpp225 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, in encodeInstruction()
228 const MCOperand &MO = MI.getOperand(OpNo); in encodeInstruction()
247 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue()
250 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
269 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue1SImm16()
272 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
292 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMMR6()
295 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
315 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueLsl2MMR6()
318 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueLsl2MMR6()
234 getBranchTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue() argument
256 getBranchTargetOpValue1SImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValue1SImm16() argument
278 getBranchTargetOpValueMMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMR6() argument
301 getBranchTargetOpValueLsl2MMR6(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueLsl2MMR6() argument
324 getBranchTarget7OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget7OpValueMM() argument
345 getBranchTargetOpValueMMPC10(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMMPC10() argument
366 getBranchTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTargetOpValueMM() argument
388 getBranchTarget21OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValue() argument
410 getBranchTarget21OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget21OpValueMM() argument
432 getBranchTarget26OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValue() argument
454 getBranchTarget26OpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchTarget26OpValueMM() argument
476 getJumpOffset16OpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpOffset16OpValue() argument
497 getJumpTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValue() argument
514 getJumpTargetOpValueMM(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getJumpTargetOpValueMM() argument
531 getUImm5Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm5Lsl2Encoding() argument
549 getSImm3Lsa2Value(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm3Lsa2Value() argument
562 getUImm6Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm6Lsl2Encoding() argument
575 getSImm9AddiuspValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSImm9AddiuspValue() argument
752 getMemEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncoding() argument
768 getMemEncodingMMImm4(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4() argument
782 getMemEncodingMMImm4Lsl1(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl1() argument
796 getMemEncodingMMImm4Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4Lsl2() argument
810 getMemEncodingMMSPImm5Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMSPImm5Lsl2() argument
825 getMemEncodingMMGPImm7Lsl2(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMGPImm7Lsl2() argument
840 getMemEncodingMMImm9(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm9() argument
854 getMemEncodingMMImm11(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm11() argument
867 getMemEncodingMMImm12(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm12() argument
891 getMemEncodingMMImm16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm16() argument
904 getMemEncodingMMImm4sp(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMemEncodingMMImm4sp() argument
932 getSizeInsEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSizeInsEncoding() argument
945 getUImmWithOffsetEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImmWithOffsetEncoding() argument
955 getSimm19Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm19Lsl2Encoding() argument
977 getSimm18Lsl3Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm18Lsl3Encoding() argument
999 getUImm3Mod8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm3Mod8Encoding() argument
1008 getUImm4AndValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getUImm4AndValue() argument
1036 getRegisterListOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue() argument
1056 getRegisterListOpValue16(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getRegisterListOpValue16() argument
1063 getMovePRegPairOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegPairOpValue() argument
1097 getMovePRegSingleOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getMovePRegSingleOpValue() argument
1120 getSimm23Lsl2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getSimm23Lsl2Encoding() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp218 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, in printPredicateOperand() argument
222 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
313 printOperand(MI, OpNo + 1, STI, O); in printPredicateOperand()
316 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo, in printATBitsAsHint() argument
319 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
326 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo, in printU1ImmOperand() argument
329 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
334 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo, in printU2ImmOperand() argument
337 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand()
342 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo, in printU3ImmOperand() argument
350 printU4ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU4ImmOperand() argument
358 printS5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS5ImmOperand() argument
366 printImmZeroOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printImmZeroOperand() argument
374 printU5ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU5ImmOperand() argument
382 printU6ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU6ImmOperand() argument
390 printU7ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU7ImmOperand() argument
401 printU8ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU8ImmOperand() argument
408 printU10ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU10ImmOperand() argument
416 printU12ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU12ImmOperand() argument
424 printS16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS16ImmOperand() argument
433 printS34ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printS34ImmOperand() argument
445 printU16ImmOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printU16ImmOperand() argument
455 printBranchOperand(const MCInst * MI,uint64_t Address,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printBranchOperand() argument
481 printAbsBranchOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printAbsBranchOperand() argument
490 printcrbitm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printcrbitm() argument
508 printMemRegImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm() argument
520 printMemRegImmHash(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImmHash() argument
529 printMemRegImm34PCRel(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34PCRel() argument
538 printMemRegImm34(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegImm34() argument
547 printMemRegReg(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printMemRegReg() argument
561 printTLSCall(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printTLSCall() argument
643 printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O) printOperand() argument
[all...]
H A DPPCInstPrinter.h50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
52 void printPredicateOperand(const MCInst *MI, unsigned OpNo,
55 void printATBitsAsHint(const MCInst *MI, unsigned OpNo,
58 void printU1ImmOperand(const MCInst *MI, unsigned OpNo,
60 void printU2ImmOperand(const MCInst *MI, unsigned OpNo,
62 void printU3ImmOperand(const MCInst *MI, unsigned OpNo,
64 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
66 void printS5ImmOperand(const MCInst *MI, unsigned OpNo,
68 void printU5ImmOperand(const MCInst *MI, unsigned OpNo,
70 void printU6ImmOperand(const MCInst *MI, unsigned OpNo,
[all …]
H A DPPCMCCodeEmitter.h38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
41 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
44 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
47 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
53 uint64_t getImm34Encoding(const MCInst &MI, unsigned OpNo,
57 uint64_t getImm34EncodingNoPCRel(const MCInst &MI, unsigned OpNo,
60 uint64_t getImm34EncodingPCRel(const MCInst &MI, unsigned OpNo,
63 unsigned getDispRIEncoding(const MCInst &MI, unsigned OpNo,
66 unsigned getDispRIXEncoding(const MCInst &MI, unsigned OpNo,
[all...]
H A DPPCMCCodeEmitter.cpp44 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, in getDirectBrEncoding()
47 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
154 unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, in getDispRIEncoding()
157 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIEncoding()
167 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, in getDispRIXEncoding()
170 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIXEncoding()
180 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, in getDispRIX16Encoding()
183 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIX16Encoding()
193 PPCMCCodeEmitter::getVSRpEvenEncoding(const MCInst &MI, unsigned OpNo,
196 assert(MI.getOperand(OpNo) in getDispRIHashEncoding()
42 getDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDirectBrEncoding() argument
60 getCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getCondBrEncoding() argument
73 getAbsDirectBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsDirectBrEncoding() argument
86 getAbsCondBrEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getAbsCondBrEncoding() argument
99 getVSRpEvenEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getVSRpEvenEncoding() argument
108 getImm16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm16Encoding() argument
120 getImm34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,MCFixupKind Fixup) const getImm34Encoding() argument
135 getImm34EncodingNoPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingNoPCRel() argument
143 getImm34EncodingPCRel(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getImm34EncodingPCRel() argument
150 getDispRIEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIEncoding() argument
164 getDispRIXEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIXEncoding() argument
178 getDispRIX16Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIX16Encoding() argument
195 getDispRIHashEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRIHashEncoding() argument
210 getDispRI34PCRelEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34PCRelEncoding() argument
293 getDispRI34Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispRI34Encoding() argument
302 getDispSPE8Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE8Encoding() argument
312 getDispSPE4Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE4Encoding() argument
322 getDispSPE2Encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getDispSPE2Encoding() argument
331 getTLSRegEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSRegEncoding() argument
351 getTLSCallEncoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getTLSCallEncoding() argument
364 get_crbitm_encoding(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const get_crbitm_encoding() argument
398 unsigned OpNo = getOpIdxForMO(MI, MO); getMachineOpValue() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp82 void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
86 const MCOperand &MO = MI->getOperand(OpNo); in printOperand()
103 unsigned OpNo, in printBranchOperand() argument
106 const MCOperand &MO = MI->getOperand(OpNo); in printBranchOperand()
108 return printOperand(MI, OpNo, STI, O); in printBranchOperand()
120 void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, in printCSRSystemRegister() argument
123 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister()
134 void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, in printFenceArg() argument
137 unsigned FenceArg = MI->getOperand(OpNo).getImm(); in printFenceArg()
152 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, in printFRMArg() argument
[all …]
H A DRISCVInstPrinter.h33 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
35 void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
37 void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
39 void printFenceArg(const MCInst *MI, unsigned OpNo,
41 void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
43 void printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
45 void printFPImmOperand(const MCInst *MI, unsigned OpNo,
47 void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
49 void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
51 void printVMaskReg(const MCInst *MI, unsigned OpNo,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaMCCodeEmitter.cpp78 uint32_t getMemRegEncoding(const MCInst &MI, unsigned OpNo,
82 uint32_t getImm8OpValue(const MCInst &MI, unsigned OpNo,
86 uint32_t getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
90 uint32_t getImm12OpValue(const MCInst &MI, unsigned OpNo,
94 uint32_t getUimm4OpValue(const MCInst &MI, unsigned OpNo,
98 uint32_t getUimm5OpValue(const MCInst &MI, unsigned OpNo,
102 uint32_t getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
106 uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
110 uint32_t getB4constOpValue(const MCInst &MI, unsigned OpNo,
114 uint32_t getB4constuOpValue(const MCInst &MI, unsigned OpNo,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp149 void LanaiInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
163 void LanaiInstPrinter::printMemImmOperand(const MCInst *MI, unsigned OpNo, in printMemImmOperand() argument
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
177 void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo, in printHi16ImmOperand() argument
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
189 void LanaiInstPrinter::printHi16AndImmOperand(const MCInst *MI, unsigned OpNo, in printHi16AndImmOperand() argument
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
201 void LanaiInstPrinter::printLo16AndImmOperand(const MCInst *MI, unsigned OpNo, in printLo16AndImmOperand() argument
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
[all …]
H A DLanaiMCCodeEmitter.cpp62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
186 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getRiMemoryOpValue() argument
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue()
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2); in getRiMemoryOpValue()
218 const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getRrMemoryOpValue() argument
221 const MCOperand Op1 = Inst.getOperand(OpNo in getRrMemoryOpValue()
256 getSplsOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getSplsOpValue() argument
289 getBranchTargetOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getBranchTargetOpValue() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kAsmPrinter.cpp67 bool M68kAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, in PrintAsmOperand() argument
71 printOperand(MI, OpNo, OS); in PrintAsmOperand()
76 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); in PrintAsmOperand()
102 unsigned OpNo, const char *ExtraCode, in PrintAsmMemoryOperand() argument
104 const MachineOperand &MO = MI->getOperand(OpNo); in PrintAsmMemoryOperand()
111 ++OpNo; in PrintAsmMemoryOperand()
115 printARIMem(MI, OpNo, OS); in PrintAsmMemoryOperand()
118 printARIPIMem(MI, OpNo, OS); in PrintAsmMemoryOperand()
121 printARIPDMem(MI, OpNo, OS); in PrintAsmMemoryOperand()
124 printARIDMem(MI, OpNo, OS); in PrintAsmMemoryOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430InstPrinter.cpp41 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, in printPCRelImmOperand() argument
43 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImmOperand()
56 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
59 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
71 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, in printSrcMemOperand() argument
74 const MCOperand &Base = MI->getOperand(OpNo); in printSrcMemOperand()
75 const MCOperand &Disp = MI->getOperand(OpNo+1); in printSrcMemOperand()
101 void MSP430InstPrinter::printIndRegOperand(const MCInst *MI, unsigned OpNo, in printIndRegOperand() argument
103 const MCOperand &Base = MI->getOperand(OpNo); in printIndRegOperand()
107 void MSP430InstPrinter::printPostIndRegOperand(const MCInst *MI, unsigned OpNo, in printPostIndRegOperand() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp293 void X86AsmPrinter::PrintOperand(const MachineInstr *MI, unsigned OpNo, in PrintOperand() argument
295 const MachineOperand &MO = MI->getOperand(OpNo); in PrintOperand()
336 void X86AsmPrinter::PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo, in PrintModifiedOperand() argument
338 const MachineOperand &MO = MI->getOperand(OpNo); in PrintModifiedOperand()
340 return PrintOperand(MI, OpNo, O); in PrintModifiedOperand()
356 void X86AsmPrinter::PrintPCRelImm(const MachineInstr *MI, unsigned OpNo, in PrintPCRelImm() argument
358 const MachineOperand &MO = MI->getOperand(OpNo); in PrintPCRelImm()
363 PrintOperand(MI, OpNo, O); in PrintPCRelImm()
374 void X86AsmPrinter::PrintLeaMemReference(const MachineInstr *MI, unsigned OpNo, in PrintLeaMemReference() argument
376 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp71 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
74 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
77 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
80 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
83 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
148 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo, in getSImm13OpValue() argument
151 const MCOperand &MO = MI.getOperand(OpNo); in getSImm13OpValue()
179 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, in getCallTargetOpValue() argument
182 const MCOperand &MO = MI.getOperand(OpNo); in getCallTargetOpValue()
206 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue() argument
219 getBranchPredTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchPredTargetOpValue() argument
232 getBranchOnRegTargetOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const getBranchOnRegTargetOpValue() argument
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp152 Instruction *findInsertionPoint(Instruction &User, unsigned OpNo);
165 bool isDominated(Instruction *NewPt, Instruction *User, unsigned OpNo,
181 bool tryAndMerge(Instruction *NewPt, Instruction *User, unsigned OpNo,
191 void computeInsertionPoint(Instruction *User, unsigned OpNo,
208 Instruction *User, unsigned OpNo, in appendAndTransferDominatedUses() argument
212 IPI->second.emplace_back(User, OpNo); in appendAndTransferDominatedUses()
372 unsigned OpNo) { in findInsertionPoint() argument
376 return PhiInst->getIncomingBlock(OpNo)->getTerminator(); in findInsertionPoint()
382 unsigned OpNo, in isDominated() argument
400 IPI.second.emplace_back(User, OpNo); in isDominated()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp101 void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo]; in printOperand()
111 if (OpNo >= MI->size()) { in printOperand()
121 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
143 void AVRInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo, in printPCRelImm() argument
145 if (OpNo >= MI->size()) { in printPCRelImm()
155 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm()
173 void AVRInstPrinter::printMemri(const MCInst *MI, unsigned OpNo, in printMemri() argument
175 assert(MI->getOperand(OpNo).isReg() && in printMemri()
178 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemri()
[all …]
H A DAVRMCCodeEmitter.cpp93 AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo, in encodeRelCondBrTarget() argument
96 const MCOperand &MO = MI.getOperand(OpNo); in encodeRelCondBrTarget()
113 unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo, in encodeLDSTPtrReg() argument
116 auto MO = MI.getOperand(OpNo); in encodeLDSTPtrReg()
137 unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo, in encodeMemri() argument
140 auto RegOp = MI.getOperand(OpNo); in encodeMemri()
141 auto OffsetOp = MI.getOperand(OpNo + 1); in encodeMemri()
174 unsigned AVRMCCodeEmitter::encodeComplement(const MCInst &MI, unsigned OpNo, in encodeComplement() argument
178 assert(MI.getOperand(OpNo).isImm()); in encodeComplement()
180 auto Imm = MI.getOperand(OpNo) in encodeComplement()
185 encodeImm(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeImm() argument
210 encodeCallTarget(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const encodeCallTarget() argument
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