78   uint32_t getMemRegEncoding(const MCInst &MI, unsigned OpNo,
82   uint32_t getImm8OpValue(const MCInst &MI, unsigned OpNo,
86   uint32_t getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,
90   uint32_t getImm12OpValue(const MCInst &MI, unsigned OpNo,
94   uint32_t getUimm4OpValue(const MCInst &MI, unsigned OpNo,
98   uint32_t getUimm5OpValue(const MCInst &MI, unsigned OpNo,
102   uint32_t getImm1_16OpValue(const MCInst &MI, unsigned OpNo,
106   uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
110   uint32_t getB4constOpValue(const MCInst &MI, unsigned OpNo,
114   uint32_t getB4constuOpValue(const MCInst &MI, unsigned OpNo,
240 XtensaMCCodeEmitter::getMemRegEncoding(const MCInst &MI, unsigned OpNo,  in getMemRegEncoding()  argument
243   assert(MI.getOperand(OpNo + 1).isImm());  in getMemRegEncoding()
245   uint32_t Res = static_cast<uint32_t>(MI.getOperand(OpNo + 1).getImm());  in getMemRegEncoding()
268   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);  in getMemRegEncoding()
273 uint32_t XtensaMCCodeEmitter::getImm8OpValue(const MCInst &MI, unsigned OpNo,  in getImm8OpValue()  argument
276   const MCOperand &MO = MI.getOperand(OpNo);  in getImm8OpValue()
285 XtensaMCCodeEmitter::getImm8_sh8OpValue(const MCInst &MI, unsigned OpNo,  in getImm8_sh8OpValue()  argument
288   const MCOperand &MO = MI.getOperand(OpNo);  in getImm8_sh8OpValue()
298 XtensaMCCodeEmitter::getImm12OpValue(const MCInst &MI, unsigned OpNo,  in getImm12OpValue()  argument
301   const MCOperand &MO = MI.getOperand(OpNo);  in getImm12OpValue()
310 XtensaMCCodeEmitter::getUimm4OpValue(const MCInst &MI, unsigned OpNo,  in getUimm4OpValue()  argument
313   const MCOperand &MO = MI.getOperand(OpNo);  in getUimm4OpValue()
322 XtensaMCCodeEmitter::getUimm5OpValue(const MCInst &MI, unsigned OpNo,  in getUimm5OpValue()  argument
325   const MCOperand &MO = MI.getOperand(OpNo);  in getUimm5OpValue()
334 XtensaMCCodeEmitter::getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,  in getShimm1_31OpValue()  argument
337   const MCOperand &MO = MI.getOperand(OpNo);  in getShimm1_31OpValue()
346 XtensaMCCodeEmitter::getImm1_16OpValue(const MCInst &MI, unsigned OpNo,  in getImm1_16OpValue()  argument
349   const MCOperand &MO = MI.getOperand(OpNo);  in getImm1_16OpValue()
358 XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,  in getB4constOpValue()  argument
361   const MCOperand &MO = MI.getOperand(OpNo);  in getB4constOpValue()
406 XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,  in getB4constuOpValue()  argument
409   const MCOperand &MO = MI.getOperand(OpNo);  in getB4constuOpValue()