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Searched refs:OpName (Results 1 – 25 of 99) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp68 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) in copyPhysReg()
131 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; in isLDSRetInstr()
225 static const R600::OpName SrcSelTable[][2] = { in getSelIdx()
226 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
227 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
228 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
229 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
230 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
231 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
232 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
[all …]
H A DGCNDPPCombine.cpp73 bool hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName, int64_t Value,
131 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
141 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
142 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
143 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
144 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0) || in isShrinkable()
145 !hasNoImmOrEqual(MI, AMDGPU::OpName::byte_sel, 0)) { in isShrinkable()
229 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
231 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
248 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
[all …]
H A DSIPeepholeSDWA.cpp365 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
366 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
369 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
370 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
453 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
454 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
456 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
460 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
461 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
462 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
[all …]
H A DGCNVOPDUtils.cpp91 const MachineOperand &Src0 = *TII.getNamedOperand(MI, AMDGPU::OpName::src0); in checkVOPDRegConstraints()
114 for (auto OpName : {AMDGPU::OpName::src1, AMDGPU::OpName::src2}) { in checkVOPDRegConstraints()
115 const MachineOperand *Src = TII.getNamedOperand(MI, OpName); in checkVOPDRegConstraints()
118 if (OpName == AMDGPU::OpName::src2) { in checkVOPDRegConstraints()
119 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::bitop3)) in checkVOPDRegConstraints()
130 for (auto OpName : {AMDGPU::OpName::clamp, AMDGPU::OpName::omod, in checkVOPDRegConstraints()
131 AMDGPU::OpName::op_sel}) { in checkVOPDRegConstraints()
132 if (TII.hasModifiersSet(MI, OpName)) in checkVOPDRegConstraints()
138 for (auto OpName : in checkVOPDRegConstraints()
139 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers, in checkVOPDRegConstraints()
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H A DR600ExpandSpecialInstrs.cpp34 R600::OpName Op);
65 R600::OpName Op) { in SetFlagInNewMI()
87 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
94 R600::OpName::pred_sel); in runOnMachineFunction()
96 R600::OpName::pred_sel); in runOnMachineFunction()
116 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
118 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
148 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
151 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1)) in runOnMachineFunction()
198 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg(); in runOnMachineFunction()
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H A DSILoadStoreOptimizer.cpp232 AMDGPU::OpName OpName, Register DestReg) const;
235 AMDGPU::OpName OpName) const;
339 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
464 if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) && in getInstClass()
465 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0)) in getInstClass()
699 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
701 AMDGPU::OpName RsrcName = in getRegs()
702 TII.isMIMG(Opc) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc; in getRegs()
834 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
838 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
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H A DGCNCreateVOPD.cpp84 const AMDGPU::OpName Mods[2][3] = { in doReplace()
85 {AMDGPU::OpName::src0X_modifiers, AMDGPU::OpName::vsrc1X_modifiers, in doReplace()
86 AMDGPU::OpName::vsrc2X_modifiers}, in doReplace()
87 {AMDGPU::OpName::src0Y_modifiers, AMDGPU::OpName::vsrc1Y_modifiers, in doReplace()
88 AMDGPU::OpName::vsrc2Y_modifiers}}; in doReplace()
89 const AMDGPU::OpName SrcMods[3] = {AMDGPU::OpName::src0_modifiers, in doReplace()
90 AMDGPU::OpName::src1_modifiers, in doReplace()
91 AMDGPU::OpName::src2_modifiers}; in doReplace()
H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
141 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
143 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1); in mergeIfPossible()
H A DAMDGPUMCInstLower.cpp128 llvm::AMDGPU::OpName OpName; in lowerT16D16Helper() local
131 OpName = llvm::AMDGPU::OpName::vdst; in lowerT16D16Helper()
133 OpName = llvm::AMDGPU::OpName::data0; in lowerT16D16Helper()
137 OpName = AMDGPU::hasNamedOperand(Opcode, llvm::AMDGPU::OpName::vdata) in lowerT16D16Helper()
138 ? llvm::AMDGPU::OpName::vdata in lowerT16D16Helper()
139 : llvm::AMDGPU::OpName::vdst; in lowerT16D16Helper()
143 int VDstOrVDataIdx = AMDGPU::getNamedOperandIdx(Opcode, OpName); in lowerT16D16Helper()
166 if (AMDGPU::hasNamedOperand(MCOpcode, AMDGPU::OpName::vdst_in)) { in lowerT16D16Helper()
216 int FIIdx = AMDGPU::getNamedOperandIdx(MCOpcode, AMDGPU::OpName::fi); in lower()
257 TII->getNamedOperand(*MI, MI->mayLoad() ? AMDGPU::OpName::vdst in emitVGPRBlockComment()
[all …]
H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
125 const R600::OpName Ops[] = {R600::OpName::src0, R600::OpName::src1, in substitutePV()
126 R600::OpName::src2}; in substitutePV()
127 for (R600::OpName Op : Ops) { in substitutePV()
179 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
180 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); in isLegalToPacketizeTogether()
213 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); in setIsLastBit()
294 R600::OpName::bank_swizzle); in addToPacket()
298 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
H A DSIInstrInfo.cpp83 AMDGPU::OpName OpName) { in nodesHaveSameOperandValue() argument
87 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
88 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
154 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::sdst); in resultDependsOnExec()
266 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
267 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
284 if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) || in areLoadsFromSameBasePtr()
285 !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase)) in areLoadsFromSameBasePtr()
318 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
319 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || in areLoadsFromSameBasePtr()
[all …]
H A DSIFoldOperands.cpp364 return OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
368 int SIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in frameIndexMayFold()
372 int VIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
418 if (AMDGPU::hasNamedOperand(NewOp, AMDGPU::OpName::clamp)) in foldCopyToVGPROfScalarAddOfFrameIndex()
502 AMDGPU::OpName ModName = AMDGPU::OpName::NUM_OPERAND_NAMES; in tryFoldImmWithOpSel()
504 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) { in tryFoldImmWithOpSel()
505 ModName = AMDGPU::OpName::src0_modifiers; in tryFoldImmWithOpSel()
507 } else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) { in tryFoldImmWithOpSel()
508 ModName = AMDGPU::OpName::src1_modifiers; in tryFoldImmWithOpSel()
510 } else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) { in tryFoldImmWithOpSel()
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H A DR600ISelLowering.cpp228 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
287 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); in EmitInstrWithCustomInserter()
298 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
1971 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in FoldOperand()
1982 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
1983 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
1984 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
1985 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
1986 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
1987 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in FoldOperand()
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H A DSILateBranchLowering.cpp144 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::exec); in expandChainCall()
158 *TII->getNamedOperand(MI, AMDGPU::OpName::numvgprs)); in expandChainCall()
162 .addDef(TII->getNamedOperand(MI, AMDGPU::OpName::src0)->getReg()); in expandChainCall()
164 *TII->getNamedOperand(MI, AMDGPU::OpName::src0)); in expandChainCall()
166 *TII->getNamedOperand(MI, AMDGPU::OpName::fbcallee)); in expandChainCall()
174 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
176 *TII->getNamedOperand(MI, AMDGPU::OpName::fbexec)); in expandChainCall()
180 *TII->getNamedOperand(MI, AMDGPU::OpName::exec)); in expandChainCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp84 AMDGPU::OpName Name) { in insertNamedMCOperand()
396 AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS) in decodeAVLdSt()
397 ? AMDGPU::OpName::data0 in decodeAVLdSt()
398 : AMDGPU::OpName::vdata; in decodeAVLdSt()
402 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeAVLdSt()
408 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); in decodeAVLdSt()
774 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != in getInstruction()
786 AMDGPU::OpName::src2_modifiers); in getInstruction()
793 AMDGPU::OpName::src2_modifiers); in getInstruction()
798 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); in getInstruction()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DPatternParser.cpp188 const StringInit *OpName) { in parseInstructionPatternOperand() argument
192 if (OpName) in parseInstructionPatternOperand()
194 "operand name is '" + OpName->getAsUnquotedString() + '\''); in parseInstructionPatternOperand()
200 std::string Name = OpName ? OpName->getAsUnquotedString() : ""; in parseInstructionPatternOperand()
227 std::string Name = OpName ? OpName->getAsUnquotedString() : ""; in parseInstructionPatternOperand()
234 if (!OpName) { in parseInstructionPatternOperand()
243 IP.addOperand(insertStrRef(OpName->getAsUnquotedString()), *Ty); in parseInstructionPatternOperand()
249 assert(OpName && "Unset w/ no OpName?"); in parseInstructionPatternOperand()
250 IP.addOperand(insertStrRef(OpName->getAsUnquotedString()), PatternType()); in parseInstructionPatternOperand()
H A DPatterns.cpp80 PatternType PatternType::getTypeOf(StringRef OpName) { in getTypeOf() argument
82 PT.Data.Str = OpName; in getTypeOf()
305 StringRef OpName = Op.getOperandName(); in addPattern() local
314 auto &Def = Table[OpName]; in addPattern()
320 DiagnoseRedef(OpName); in addPattern()
458 StringRef OpName = Op.getOperandName(); in check() local
459 auto &Info = Types[OpName]; in check()
462 Info.PrintTypeSrcNote = [this, OpName, Ty, &P]() { in check()
463 PrintSeenWithTypeIn(P, OpName, Ty); in check()
472 PrintSeenWithTypeIn(P, OpName, Ty); in check()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1832 bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
2341 AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::imm); in addLiteralImmOperand()
3611 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3797 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1; in getSrcOperandIndices()
3801 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immX) : -1; in getSrcOperandIndices()
3803 return {getNamedOperandIdx(Opcode, OpName::src0X), in getSrcOperandIndices()
3804 getNamedOperandIdx(Opcode, OpName::vsrc1X), in getSrcOperandIndices()
3805 getNamedOperandIdx(Opcode, OpName::vsrc2X), in getSrcOperandIndices()
3806 getNamedOperandIdx(Opcode, OpName::src0Y), in getSrcOperandIndices()
3807 getNamedOperandIdx(Opcode, OpName::vsrc1Y), in getSrcOperandIndices()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DGlobalISelCombinerEmitter.cpp270 StringRef OpName,
294 const auto OpName = Ty.getTypeOfOpName(); in processApplyPattern() local
295 if (MatchOpTable.lookup(OpName).Found) in processApplyPattern()
298 PrintError(RuleDef.getLoc(), "'" + OpName + "' ('" + Ty.str() + in processApplyPattern()
425 const InstructionPattern &IP, StringRef OpName, in inferNamedOperandType() argument
435 for (auto It = TECs.findLeader(OpName); It != TECs.member_end(); ++It) { in inferNamedOperandType()
436 if (!AllowSelf && *It == OpName) in inferNamedOperandType()
548 const auto OpName = Op.getOperandName(); in getInstEqClasses() local
550 errs() << Sep << OpName; in getInstEqClasses()
555 OutTECs.insert((Leader = OpName)); in getInstEqClasses()
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H A DDXILEmitter.cpp50 std::string OpName; // name of DXIL operation member
108 OpName = R->getNameInitAsString(); in DXILOperationDesc()
156 OpName + " is required"); in DXILOperationDesc()
177 OpName); in DXILOperationDesc()
331 OS << "DXIL_OPCODE(" << Op.OpCode << ", " << Op.OpName << ")\n"; in emitDXILOpCodes()
393 OS << "DXIL_OP_ATTRIBUTES(dxil::OpCode::" << Op.OpName << ", "; in emitDXILOpAttributes()
421 OS << "DXIL_OP_FUNCTION_TYPE(dxil::OpCode::" << Op.OpName; in emitDXILOpFunctionTypes()
445 OS << "DXIL_OP_INTRINSIC(dxil::OpCode::" << Op.OpName in emitDXILIntrinsicMap()
487 OpStrings.add(Op.OpName); in emitDXILOperationTable()
505 OS << Prefix << " { dxil::OpCode::" << Op.OpName << ", " in emitDXILOperationTable()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp356 if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel_hi)) { in getImplicitOpSelHiEncoding()
357 if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)) in getImplicitOpSelHiEncoding()
359 if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1)) in getImplicitOpSelHiEncoding()
361 if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0)) in getImplicitOpSelHiEncoding()
388 !AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::matrix_b_reuse)) { in encodeInstruction()
411 AMDGPU::OpName::vaddr0); in encodeInstruction()
413 AMDGPU::OpName::srsrc); in encodeInstruction()
431 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm)) in encodeInstruction()
620 AMDGPU::OpName::src0_modifiers)) { in getMachineOpValueT16()
621 SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in getMachineOpValueT16()
[all …]
H A DAMDGPUInstPrinter.cpp288 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format); in printSymbolicFormat()
687 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in printOperand()
852 AMDGPU::OpName::src1)) in printRegularOperand()
859 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset); in printRegularOperand()
913 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1)) in printOperandAndFPInputMods()
942 AMDGPU::OpName::src1)) in printOperandAndIntInputMods()
1128 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en); in printExpSrcN()
1131 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr); in printExpSrcN()
1209 std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = { in printPackedModifier()
1210 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0}, in printPackedModifier()
[all …]
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DSubtargetFeatureInfo.cpp143 StringRef OpName = Op->getDef()->getName(); in emitFeaturesAux() local
144 if (OpName == "not" && D->getNumArgs() == 1) { in emitFeaturesAux()
148 if ((OpName == "any_of" || OpName == "all_of") && D->getNumArgs() > 0) { in emitFeaturesAux()
152 ListSeparator LS(OpName == "any_of" ? " || " : " && "); in emitFeaturesAux()
H A DCodeGenInstruction.cpp235 StringRef OpName = Op.substr(1); in ParseOperandName() local
239 StringRef::size_type DotIdx = OpName.find_first_of('.'); in ParseOperandName()
241 SubOpName = OpName.substr(DotIdx + 1); in ParseOperandName()
246 OpName = OpName.substr(0, DotIdx); in ParseOperandName()
249 if (auto SubOp = findSubOperandAlias(OpName)) { in ParseOperandName()
256 OpName + "'"); in ParseOperandName()
261 unsigned OpIdx = getOperandNamed(OpName); in ParseOperandName()
411 StringRef OpName; in ProcessDisableEncoding() local
412 std::tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t"); in ProcessDisableEncoding()
413 if (OpName.empty()) in ProcessDisableEncoding()
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/freebsd/contrib/llvm-project/clang/lib/Tooling/Transformer/
H A DParsing.cpp244 std::string OpName = std::move(Id->Value); in parseRangeSelectorImpl() local
245 if (auto Op = findOptional(getUnaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
248 if (auto Op = findOptional(getUnaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
251 if (auto Op = findOptional(getBinaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
254 if (auto Op = findOptional(getBinaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
257 return makeParseError(State, "unknown selector name: " + OpName); in parseRangeSelectorImpl()

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