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Searched refs:OpName (Results 1 – 25 of 92) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp69 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) in copyPhysReg()
135 return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; in isLDSRetInstr()
235 {R600::OpName::src0, R600::OpName::src0_sel}, in getSelIdx()
236 {R600::OpName::src1, R600::OpName::src1_sel}, in getSelIdx()
237 {R600::OpName::src2, R600::OpName::src2_sel}, in getSelIdx()
238 {R600::OpName::src0_X, R600::OpName::src0_sel_X}, in getSelIdx()
239 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, in getSelIdx()
240 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, in getSelIdx()
241 {R600::OpName::src0_W, R600::OpName::src0_sel_W}, in getSelIdx()
242 {R600::OpName::src1_X, R600::OpName::src1_sel_X}, in getSelIdx()
[all …]
H A DSIPeepholeSDWA.cpp316 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
317 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
320 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
321 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
386 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
387 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
389 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
393 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
394 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
395 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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H A DGCNDPPCombine.cpp130 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
140 if (!hasNoImmOrEqual(MI, AMDGPU::OpName::src0_modifiers, 0, Mask) || in isShrinkable()
141 !hasNoImmOrEqual(MI, AMDGPU::OpName::src1_modifiers, 0, Mask) || in isShrinkable()
142 !hasNoImmOrEqual(MI, AMDGPU::OpName::clamp, 0) || in isShrinkable()
143 !hasNoImmOrEqual(MI, AMDGPU::OpName::omod, 0) || in isShrinkable()
144 !hasNoImmOrEqual(MI, AMDGPU::OpName::byte_sel, 0)) { in isShrinkable()
223 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask); in createDPPInst()
225 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask); in createDPPInst()
242 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { in createDPPInst()
246 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::sdst)) { in createDPPInst()
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H A DR600ExpandSpecialInstrs.cpp86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
93 R600::OpName::pred_sel); in runOnMachineFunction()
95 R600::OpName::pred_sel); in runOnMachineFunction()
115 TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1); in runOnMachineFunction()
117 TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1); in runOnMachineFunction()
147 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
150 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1)) in runOnMachineFunction()
197 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg(); in runOnMachineFunction()
199 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); in runOnMachineFunction()
204 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1); in runOnMachineFunction()
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H A DSILoadStoreOptimizer.cpp230 MachineBasicBlock::iterator InsertBefore, int OpName,
234 int OpName) const;
335 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
452 if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) && in getInstClass()
453 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0)) in getInstClass()
671 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
674 TII.isMIMG(Opc) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc; in getRegs()
798 DMask = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
802 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
807 Format = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
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H A DR600ClauseMergePass.cpp79 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
86 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
92 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in cleanPotentialDisabledCFAlu()
111 int CntIdx = TII->getOperandIdx(R600::CF_ALU, R600::OpName::COUNT); in mergeIfPossible()
123 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE0); in mergeIfPossible()
125 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK0); in mergeIfPossible()
127 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR0); in mergeIfPossible()
139 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_MODE1); in mergeIfPossible()
141 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_BANK1); in mergeIfPossible()
143 TII->getOperandIdx(R600::CF_ALU, R600::OpName::KCACHE_ADDR1); in mergeIfPossible()
H A DR600Packetizer.cpp81 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write); in getPreviousVector()
84 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); in getPreviousVector()
126 R600::OpName::src0, in substitutePV()
127 R600::OpName::src1, in substitutePV()
128 R600::OpName::src2 in substitutePV()
182 int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel), in isLegalToPacketizeTogether()
183 OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel); in isLegalToPacketizeTogether()
216 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last); in setIsLastBit()
297 R600::OpName::bank_swizzle); in addToPacket()
301 TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle); in addToPacket()
H A DSIFoldOperands.cpp187 return OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
191 int SIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr); in frameIndexMayFold()
195 int VIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in frameIndexMayFold()
252 if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) { in tryFoldImmWithOpSel()
253 ModIdx = AMDGPU::OpName::src0_modifiers; in tryFoldImmWithOpSel()
255 } else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) { in tryFoldImmWithOpSel()
256 ModIdx = AMDGPU::OpName::src1_modifiers; in tryFoldImmWithOpSel()
258 } else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) { in tryFoldImmWithOpSel()
259 ModIdx = AMDGPU::OpName::src2_modifiers; in tryFoldImmWithOpSel()
337 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::clamp); in tryFoldImmWithOpSel()
[all …]
H A DSIInstrInfo.cpp82 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) { in nodesHaveSameOperandValue() argument
86 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName); in nodesHaveSameOperandValue()
87 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); in nodesHaveSameOperandValue()
260 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
261 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); in areLoadsFromSameBasePtr()
278 if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) || in areLoadsFromSameBasePtr()
279 !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase)) in areLoadsFromSameBasePtr()
312 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
313 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) || in areLoadsFromSameBasePtr()
314 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc)) in areLoadsFromSameBasePtr()
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H A DR600ISelLowering.cpp224 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in EmitInstrWithCustomInserter()
283 int Idx = TII->getOperandIdx(*MIB, R600::OpName::literal); in EmitInstrWithCustomInserter()
294 TII->setImmOperand(*NewMI, R600::OpName::src0_sel, in EmitInstrWithCustomInserter()
1966 bool HasDst = TII->getOperandIdx(Opcode, R600::OpName::dst) > -1; in FoldOperand()
1977 TII->getOperandIdx(Opcode, R600::OpName::src0), in FoldOperand()
1978 TII->getOperandIdx(Opcode, R600::OpName::src1), in FoldOperand()
1979 TII->getOperandIdx(Opcode, R600::OpName::src2), in FoldOperand()
1980 TII->getOperandIdx(Opcode, R600::OpName::src0_X), in FoldOperand()
1981 TII->getOperandIdx(Opcode, R600::OpName::src0_Y), in FoldOperand()
1982 TII->getOperandIdx(Opcode, R600::OpName::src0_Z), in FoldOperand()
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H A DVOPCInstructions.td185 class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
186 VOP_SDWA_Pseudo <OpName, P, pattern> {
192 string Asm32 = ps.Pfl.Asm32, string real_name = ps.OpName,
1171 class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
1172 : VOP_DPP_Base<OpName, P, P.InsDPP16, " " #P.AsmDPP16>,
1202 class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
1203 : VOP_DPP8_Base<OpName, P, P.InsDPP8, " " #P.AsmDPP8>,
1220 class VOPC_DPP16<bits<8> op, VOP_DPP_Pseudo ps, string opName = ps.OpName>
1233 string opName = ps.OpName>
1236 class VOPC_DPP8<bits<8> op, VOPC_Pseudo ps, string opName = ps.OpName>
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H A DGCNHazardRecognizer.cpp156 AMDGPU::OpName::gds); in isSendMsgTraceDataOrGDS()
180 AMDGPU::OpName::simm16); in getHWReg()
820 int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
833 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
846 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc); in createsVALUHazard()
853 int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata); in createsVALUHazard()
897 Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg(); in checkVALUHazards()
921 if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel)) in checkVALUHazards()
925 if (!AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::op_sel) || in checkVALUHazards()
926 !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers) in checkVALUHazards()
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H A DSIOptimizeExecMaskingPreRA.cpp154 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
155 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
169 if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) || in optimizeVcndVcmpPair()
170 TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers)) in optimizeVcndVcmpPair()
173 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
174 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
175 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
H A DSIInsertWaitcnts.cpp808 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr); in updateByEvent()
816 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::data0)) { in updateByEvent()
819 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0), in updateByEvent()
822 if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::data1)) { in updateByEvent()
825 AMDGPU::OpName::data1), in updateByEvent()
844 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
849 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
858 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
871 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data), in updateByEvent()
878 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdst), in updateByEvent()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp404 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeAVLdSt()
405 : AMDGPU::OpName::vdata; in decodeAVLdSt()
409 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); in decodeAVLdSt()
415 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); in decodeAVLdSt()
624 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != in getInstruction()
634 AMDGPU::OpName::src2_modifiers); in getInstruction()
641 AMDGPU::OpName::src2_modifiers); in getInstruction()
646 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); in getInstruction()
652 AMDGPU::OpName::cpol); in getInstruction()
659 AMDGPU::OpName::cpol); in getInstruction()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DGlobalISelCombinerEmitter.cpp277 StringRef OpName,
301 const auto OpName = Ty.getTypeOfOpName(); in processApplyPattern() local
302 if (MatchOpTable.lookup(OpName).Found) in processApplyPattern()
305 PrintError(RuleDef.getLoc(), "'" + OpName + "' ('" + Ty.str() + in processApplyPattern()
432 const InstructionPattern &IP, StringRef OpName, in inferNamedOperandType() argument
442 for (auto It = TECs.findLeader(OpName); It != TECs.member_end(); ++It) { in inferNamedOperandType()
443 if (!AllowSelf && *It == OpName) in inferNamedOperandType()
554 const auto OpName = Op.getOperandName(); in getInstEqClasses() local
556 errs() << Sep << OpName; in getInstEqClasses()
561 OutTECs.insert((Leader = OpName)); in getInstEqClasses()
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H A DDXILEmitter.cpp38 std::string OpName; // name of DXIL operation member
112 OpName = R->getNameInitAsString(); in DXILOperationDesc()
297 OS << Op.OpName << " = " << Op.OpCode << ", // " << Op.Doc << "\n"; in emitDXILEnums()
328 OS << " { Intrinsic::" << Op.Intrinsic << ", dxil::OpCode::" << Op.OpName in emitDXILIntrinsicMap()
371 OpStrings.add(Op.OpName); in emitDXILOperationTable()
411 OS << " { dxil::OpCode::" << Op.OpName << ", " << OpStrings.get(Op.OpName) in emitDXILOperationTable()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/GlobalISel/
H A DPatternParser.cpp199 const StringInit *OpName) { in parseInstructionPatternOperand() argument
203 if (OpName) in parseInstructionPatternOperand()
205 "operand name is '" + OpName->getAsUnquotedString() + '\''); in parseInstructionPatternOperand()
211 std::string Name = OpName ? OpName->getAsUnquotedString() : ""; in parseInstructionPatternOperand()
238 std::string Name = OpName ? OpName->getAsUnquotedString() : ""; in parseInstructionPatternOperand()
245 if (!OpName) { in parseInstructionPatternOperand()
254 IP.addOperand(insertStrRef(OpName->getAsUnquotedString()), *Ty); in parseInstructionPatternOperand()
260 assert(OpName && "Unset w/ no OpName?"); in parseInstructionPatternOperand()
261 IP.addOperand(insertStrRef(OpName->getAsUnquotedString()), PatternType()); in parseInstructionPatternOperand()
H A DPatterns.cpp53 PatternType PatternType::getTypeOf(StringRef OpName) { in getTypeOf() argument
55 PT.Data.Str = OpName; in getTypeOf()
267 StringRef OpName = Op.getOperandName(); in addPattern() local
276 auto &Def = Table[OpName]; in addPattern()
282 DiagnoseRedef(OpName); in addPattern()
420 StringRef OpName = Op.getOperandName(); in check() local
421 auto &Info = Types[OpName]; in check()
424 Info.PrintTypeSrcNote = [this, OpName, Ty, &P]() { in check()
425 PrintSeenWithTypeIn(P, OpName, Ty); in check()
434 PrintSeenWithTypeIn(P, OpName, Ty); in check()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DSubtargetFeatureInfo.cpp145 StringRef OpName = Op->getDef()->getName(); in emitFeaturesAux() local
146 if (OpName == "not" && D->getNumArgs() == 1) { in emitFeaturesAux()
150 if ((OpName == "any_of" || OpName == "all_of") && D->getNumArgs() > 0) { in emitFeaturesAux()
154 ListSeparator LS(OpName == "any_of" ? " || " : " && "); in emitFeaturesAux()
H A DCodeGenInstruction.cpp238 StringRef OpName = Op.substr(1); in ParseOperandName() local
242 StringRef::size_type DotIdx = OpName.find_first_of('.'); in ParseOperandName()
244 SubOpName = OpName.substr(DotIdx + 1); in ParseOperandName()
249 OpName = OpName.substr(0, DotIdx); in ParseOperandName()
254 if (std::pair<unsigned, unsigned> SubOp; hasSubOperandAlias(OpName, SubOp)) { in ParseOperandName()
261 OpName + "'"); in ParseOperandName()
266 OpIdx = getOperandNamed(OpName); in ParseOperandName()
414 StringRef OpName; in ProcessDisableEncoding() local
415 std::tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t"); in ProcessDisableEncoding()
416 if (OpName.empty()) in ProcessDisableEncoding()
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/freebsd/contrib/llvm-project/clang/lib/Tooling/Transformer/
H A DParsing.cpp251 std::string OpName = std::move(Id->Value); in parseRangeSelectorImpl() local
252 if (auto Op = findOptional(getUnaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
255 if (auto Op = findOptional(getUnaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
258 if (auto Op = findOptional(getBinaryStringSelectors(), OpName)) in parseRangeSelectorImpl()
261 if (auto Op = findOptional(getBinaryRangeSelectors(), OpName)) in parseRangeSelectorImpl()
264 return makeParseError(State, "unknown selector name: " + OpName); in parseRangeSelectorImpl()
H A DStencil.cpp120 StringRef OpName; in toString() local
123 OpName = "expression"; in toString()
126 OpName = "deref"; in toString()
129 OpName = "maybeDeref"; in toString()
132 OpName = "addressOf"; in toString()
135 OpName = "maybeAddressOf"; in toString()
138 OpName = "describe"; in toString()
141 return (OpName + "(\"" + Id + "\")").str(); in toString()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1751 bool validateNeg(const MCInst &Inst, int OpName);
3471 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
3658 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1; in getSrcOperandIndices()
3662 AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred) in getSrcOperandIndices()
3665 return {getNamedOperandIdx(Opcode, OpName::src0X), in getSrcOperandIndices()
3666 getNamedOperandIdx(Opcode, OpName::vsrc1X), in getSrcOperandIndices()
3667 getNamedOperandIdx(Opcode, OpName::src0Y), in getSrcOperandIndices()
3668 getNamedOperandIdx(Opcode, OpName::vsrc1Y), in getSrcOperandIndices()
3673 return {getNamedOperandIdx(Opcode, OpName::src0), in getSrcOperandIndices()
3674 getNamedOperandIdx(Opcode, OpName::src1), in getSrcOperandIndices()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp344 using namespace AMDGPU::OpName; in getImplicitOpSelHiEncoding()
399 AMDGPU::OpName::vaddr0); in encodeInstruction()
401 AMDGPU::OpName::srsrc); in encodeInstruction()
419 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm)) in encodeInstruction()
618 AMDGPU::OpName::src0_modifiers)) { in getMachineOpValueT16()
619 SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in getMachineOpValueT16()
621 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst); in getMachineOpValueT16()
628 MI.getOpcode(), AMDGPU::OpName::src1_modifiers)) in getMachineOpValueT16()
629 SrcMOIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src1); in getMachineOpValueT16()
631 MI.getOpcode(), AMDGPU::OpName::src2_modifiers)) in getMachineOpValueT16()
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