156                                            AMDGPU::OpName::gds);  in isSendMsgTraceDataOrGDS()
180                                                      AMDGPU::OpName::simm16);  in getHWReg()
820   int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);  in createsVALUHazard()
833         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);  in createsVALUHazard()
846     int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);  in createsVALUHazard()
853     int DataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);  in createsVALUHazard()
897       Register Def = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)->getReg();  in checkVALUHazards()
921         if (auto *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel))  in checkVALUHazards()
925         if (!AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::op_sel) ||  in checkVALUHazards()
926             !(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)  in checkVALUHazards()
932       if (auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) {  in checkVALUHazards()
989       MachineOperand *Src = TII.getNamedOperand(*VALU, AMDGPU::OpName::src0);  in checkVALUHazards()
1056       TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1);  in checkRWLaneHazards()
1136   auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);  in fixVcmpxPermlaneHazards()
1206     SDSTName = AMDGPU::OpName::vdst;  in fixSMEMtoVectorWriteHazards()
1209     SDSTName = AMDGPU::OpName::sdst;  in fixSMEMtoVectorWriteHazards()
1302       if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst))  in fixVcmpxExecWARHazard()
1413   const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst);  in fixLdsDirectVALUHazard()
1446       TII.getNamedOperand(*MI, AMDGPU::OpName::waitvdst);  in fixLdsDirectVALUHazard()
1456   const MachineOperand *VDST = TII.getNamedOperand(*MI, AMDGPU::OpName::vdst);  in fixLdsDirectVMEMHazard()
1474             !TII.getNamedOperand(I, AMDGPU::OpName::waitvsrc)->getImm());  in fixLdsDirectVMEMHazard()
1482     TII.getNamedOperand(*MI, AMDGPU::OpName::waitvsrc)->setImm(0);  in fixLdsDirectVMEMHazard()
1735         TII->getNamedOperand(*MI, AMDGPU::OpName::src0)->getReg();  in fixWMMAHazards()
1737         TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg();  in fixWMMAHazards()
1740         TII->getNamedOperand(I, AMDGPU::OpName::vdst)->getReg();  in fixWMMAHazards()
1752             TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg();  in fixWMMAHazards()
1789   MachineOperand *Amt = TII.getNamedOperand(*MI, AMDGPU::OpName::src0);  in fixShift64HighRegBug()
1802   MachineOperand *Src1 = TII.getNamedOperand(*MI, AMDGPU::OpName::src1);  in fixShift64HighRegBug()
1888   const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset);  in checkNSAtoVMEMHazard()
2046     int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);  in checkMAIHazards908()
2114       Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg();  in checkMAIHazards908()
2199   int SrcCIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);  in checkMAIHazards90A()
2504                                            AMDGPU::OpName::src2);  in checkMAIVALUHazards()
2704           TII.getNamedOperand(MI, AMDGPU::OpName::src2);  in checkMAIVALUHazards()
2780   const MachineOperand *SDSTOp = TII.getNamedOperand(*MI, AMDGPU::OpName::sdst);  in fixVALUMaskWriteHazard()
2820       const MachineOperand *SSRCOp = TII.getNamedOperand(I, AMDGPU::OpName::src2);  in fixVALUMaskWriteHazard()