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Searched refs:Op3 (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp235 unsigned &Op3) { in Decode3OpInstruction() argument
245 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
514 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
515 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
519 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
527 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
528 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
532 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
540 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
541 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h27 SDValue Op3, Align Alignment, bool isVolatile,
33 SDValue Op1, SDValue Op2, SDValue Op3,
39 SDValue Op3, Align Alignment, bool IsVolatile,
H A DWebAssemblySelectionDAGInfo.cpp38 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
H A DSelectionDAG.h1612 SDValue Op3);
1614 SDValue Op3, SDValue Op4);
1616 SDValue Op3, SDValue Op4, SDValue Op5);
1644 SDValue Op1, SDValue Op2, SDValue Op3);
1679 SDValue Op1, SDValue Op2, SDValue Op3);
1685 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1692 SDValue Op3);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h110 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
111 if (Op3.isGlobal()) in getAddressFromInstr()
112 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
H A DX86FastISel.cpp169 unsigned Op1, unsigned Op2, unsigned Op3);
4040 unsigned Op2, unsigned Op3) { in fastEmitInst_rrrr() argument
4047 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
4054 .addReg(Op3); in fastEmitInst_rrrr()
4060 .addReg(Op3); in fastEmitInst_rrrr()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h24 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h57 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp332 MachineInstr *Op3 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); in matchFPMed3ToClamp() local
333 if (Op3->getOpcode() == TargetOpcode::G_FCONSTANT) in matchFPMed3ToClamp()
334 return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0); in matchFPMed3ToClamp()
H A DR600InstrFormats.td28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp293 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
294 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
300 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1697 T2 Op3; member
1699 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1700 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1706 Op3.match(I->getOperand(2)); in match()
2548 const Opnd3 &Op3) {
2549 return m_Intrinsic<Intrinsic::masked_load>(Op0, Op1, Op2, Op3);
2556 const Opnd3 &Op3) {
2557 return m_Intrinsic<Intrinsic::masked_gather>(Op0, Op1, Op2, Op3);
2580 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
2581 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td421 : Pat<(vtd (op pg:$Op1, vts:$Op2, vtd:$Op3)),
422 (inst $Op3, $Op1, $Op2)>;
429 def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, vtd:$Op3)),
430 (inst $Op3, $Op1, $Op2)>;
437 : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), vtd:$Op3)),
438 (inst $Op3, $Op1, $Op2)>;
444 def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, (i64 timm0_1), vtd:$Op3)),
445 (inst $Op3, $Op1, $Op2)>;
487 : Pat<(vtd (op (pt (SVEAllActive:$Op1)), vt1:$Op2, vt2:$Op3)),
488 (inst $Op1, $Op2, $Op3)>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp106 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
110 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
113 switch (Op3.getImm()) { in printInst()
148 if (Op2.isImm() && Op3.isImm()) { in printInst()
152 int64_t imms = Op3.getImm(); in printInst()
186 if (Op2.getImm() > Op3.getImm()) { in printInst()
194 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; in printInst()
207 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1; in printInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp6221 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
6222 if (Op2.isScalarReg() && Op3.isImm()) { in MatchAndEmitInstruction()
6223 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
6243 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in MatchAndEmitInstruction()
6244 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in MatchAndEmitInstruction()
6245 Op3.getEndLoc(), getContext()); in MatchAndEmitInstruction()
6307 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in MatchAndEmitInstruction() local
6310 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in MatchAndEmitInstruction()
6311 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in MatchAndEmitInstruction()
6326 return Error(Op3.getStartLoc(), in MatchAndEmitInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1344 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1348 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1352 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1368 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1376 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1386 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1390 .add(Op3); in expandPostRAPseudo()
1401 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1409 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1422 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
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H A DHexagonSplitDouble.cpp903 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
904 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
905 int64_t Sh64 = Op3.getImm(); in splitAslOr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h136 MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp233 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
240 TmpInst.addOperand(Op3); in emitRRRX()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp10535 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
10536 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
10542 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
10543 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
10549 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
10550 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
10643 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
10645 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
10850 SDValue Op3) { in getMachineNode() argument
10852 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
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H A DSelectionDAGBuilder.cpp6457 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6466 SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol, in visitIntrinsicCall()
6499 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6505 Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, in visitIntrinsicCall()
6531 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
6540 SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, &I, in visitIntrinsicCall()
7217 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
7219 Op1.getValueType(), Op1, Op2, Op3)); in visitIntrinsicCall()
7228 SDValue Op3 = getValue(I.getArgOperand(2)); in visitIntrinsicCall() local
7230 Op1, Op2, Op3, DAG, TLI)); in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6766 const auto &Op3 = static_cast<ARMOperand &>(*Operands[MnemonicOpsEndInd]); in tryConvertingToTwoOperandForm() local
6768 if (!Op3.isReg() || !Op4.isReg()) in tryConvertingToTwoOperandForm()
6771 auto Op3Reg = Op3.getReg(); in tryConvertingToTwoOperandForm()
6937 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[IdX + 1]); in fixupGNULDRDAlias() local
6941 if (!Op3.isGPRMem()) in fixupGNULDRDAlias()
7017 const MCParsedAsmOperand &Op3 = *Operands[MnemonicOpsEndInd + 2]; in CDEConvertDualRegOperand() local
7018 if (!Op3.isReg() || Op3.getReg() != RNext) in CDEConvertDualRegOperand()
7019 return Error(Op3.getStartLoc(), "operand must be a consecutive register"); in CDEConvertDualRegOperand()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DVerifier.cpp5932 auto *Op3 = cast<ConstantInt>(Call.getArgOperand(2)); in visitIntrinsicCall() local
5933 Check(Op3->getType()->isIntegerTy(), in visitIntrinsicCall()
5935 Check(Op3->getBitWidth() <= 32, in visitIntrinsicCall()
5940 Check(Op3->getZExtValue() < Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
5944 Check(Op3->getZExtValue() <= Op1->getType()->getScalarSizeInBits(), in visitIntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DConstantFolding.cpp3105 if (const auto *Op3 = dyn_cast<ConstantFP>(Operands[2])) { in ConstantFoldScalarCall3() local
3108 const APFloat &C3 = Op3->getValueAPF(); in ConstantFoldScalarCall3()

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