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Searched refs:Op3 (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp236 unsigned &Op3) { in Decode3OpInstruction() argument
246 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode3OpInstruction()
515 unsigned Op1, Op2, Op3; in Decode3RInstruction() local
516 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RInstruction()
520 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RInstruction()
528 unsigned Op1, Op2, Op3; in Decode3RImmInstruction() local
529 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode3RImmInstruction()
533 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); in Decode3RImmInstruction()
541 unsigned Op1, Op2, Op3; in Decode2RUSInstruction() local
542 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); in Decode2RUSInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h30 SDValue Op3, Align Alignment, bool isVolatile,
36 SDValue Op1, SDValue Op2, SDValue Op3,
42 SDValue Op3, Align Alignment, bool IsVolatile,
H A DWebAssemblySelectionDAGInfo.cpp54 SDValue Op3, Align Alignment, bool IsVolatile, in EmitTargetCodeForMemmove() argument
56 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h77 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
93 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
107 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
120 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
H A DSelectionDAG.h1736 SDValue Op3);
1738 SDValue Op3, SDValue Op4);
1740 SDValue Op3, SDValue Op4, SDValue Op5);
1770 SDValue Op1, SDValue Op2, SDValue Op3);
1808 SDValue Op3);
1816 SDValue Op2, SDValue Op3);
1825 SDValue Op2, SDValue Op3);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h104 const MachineOperand &Op3 = MI->getOperand(Operand + 3); in getAddressFromInstr() local
105 if (Op3.isGlobal()) in getAddressFromInstr()
106 AM.GV = Op3.getGlobal(); in getAddressFromInstr()
108 AM.Disp = Op3.getImm(); in getAddressFromInstr()
H A DX86FastISel.cpp170 Register Op1, Register Op2, Register Op3);
4055 Register Op2, Register Op3) { in fastEmitInst_rrrr() argument
4062 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
4069 .addReg(Op3); in fastEmitInst_rrrr()
4075 .addReg(Op3); in fastEmitInst_rrrr()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp653 Value *Op3 = EmitScalarExpr(E->getArg(3)); in EmitPPCBuiltinExpr() local
661 return Builder.CreateOr(Builder.CreateAnd(Shift, Op3), in EmitPPCBuiltinExpr()
662 Builder.CreateAnd(Op1, Builder.CreateNot(Op3))); in EmitPPCBuiltinExpr()
668 {Op0, Op1, Op2, Op3}); in EmitPPCBuiltinExpr()
1298 Value *Op3 = EmitScalarExpr(E->getArg(3)); in EmitPPCBuiltinExpr() local
1300 {Op0, Op1, Op2, Op3}); in EmitPPCBuiltinExpr()
1306 Value *Op3 = EmitScalarExpr(E->getArg(3)); in EmitPPCBuiltinExpr() local
1308 {Op0, Op1, Op2, Op3}); in EmitPPCBuiltinExpr()
1314 Value *Op3 = EmitScalarExpr(E->getArg(3)); in EmitPPCBuiltinExpr() local
1316 {Op0, Op1, Op2, Op3}); in EmitPPCBuiltinExpr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.h29 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp296 BPFOperand &Op3 = (BPFOperand &)*Operands[3]; in PreMatchCheck() local
297 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
303 && Op0.getReg() != Op3.getReg()) in PreMatchCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h59 SDValue Op3, Align Alignment, bool isVolatile,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankCombiner.cpp332 MachineInstr *Op3 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); in matchFPMed3ToClamp() local
333 if (Op3->getOpcode() == TargetOpcode::G_FCONSTANT) in matchFPMed3ToClamp()
334 return Op3->getOperand(1).getFPImm()->isExactlyValue(0.0); in matchFPMed3ToClamp()
H A DR600InstrFormats.td28 bit Op3 = 0;
54 let TSFlags{5} = Op3;
H A DAMDGPURegBankLegalizeHelper.cpp349 auto Op3 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(3).getReg()); in lowerSplitTo32Select() local
353 B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(0), Op3.getReg(0), Flags); in lowerSplitTo32Select()
355 B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(1), Op3.getReg(1), Flags); in lowerSplitTo32Select()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h359 const Op3_t &Op3) { in m_VPInstruction() argument
361 {Op0, Op1, Op2, Op3}); in m_VPInstruction()
631 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
632 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1794 T2 Op3; member
1796 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1797 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1804 if (Op2.match(I->getOperand(1)) && Op3.match(I->getOperand(2))) in match()
1807 Op3.match(I->getOperand(1)); in match()
2692 const Opnd3 &Op3) {
2693 return m_Intrinsic<Intrinsic::masked_load>(Op0, Op1, Op2, Op3);
2700 const Opnd3 &Op3) {
2701 return m_Intrinsic<Intrinsic::masked_gather>(Op0, Op1, Op2, Op3);
2724 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td492 : Pat<(vtd (op pg:$Op1, vts:$Op2, vtd:$Op3)),
493 (inst $Op3, $Op1, $Op2)>;
500 def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, vtd:$Op3)),
501 (inst $Op3, $Op1, $Op2)>;
518 : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), vtd:$Op3)),
519 (inst $Op3, $Op1, $Op2)>;
525 def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, (i64 timm0_1), vtd:$Op3)),
526 (inst $Op3, $Op1, $Op2)>;
565 : Pat<(vtd (op (pt (SVEAllActive:$Op1)), vt1:$Op2, vt2:$Op3)),
566 (inst $Op1, $Op2, $Op3)>;
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H A DAArch64SVEInstrInfo.td594 def AArch64bsl : PatFrags<(ops node:$Op1, node:$Op2, node:$Op3),
595 [(AArch64bsp node:$Op3, node:$Op1, node:$Op2),
596 (or (and node:$Op1, node:$Op3), (and node:$Op2, (vnot node:$Op3)))]>;
598 def AArch64bsl1n : PatFrag<(ops node:$Op1, node:$Op2, node:$Op3),
599 (AArch64bsl (vnot node:$Op1), node:$Op2, node:$Op3)>;
601 def AArch64bsl2n : PatFrags<(ops node:$Op1, node:$Op2, node:$Op3),
602 [(AArch64bsl node:$Op1, (vnot node:$Op2), node:$Op3),
603 (or (and node:$Op1, node:$Op3), (vnot (or node:$Op2, node:$Op3)))]>;
605 def AArch64nbsl : PatFrag<(ops node:$Op1, node:$Op2, node:$Op3),
606 (vnot (AArch64bsl node:$Op1, node:$Op2, node:$Op3))>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp105 const MCOperand &Op3 = MI->getOperand(3); in printInst() local
109 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
112 switch (Op3.getImm()) { in printInst()
147 if (Op2.isImm() && Op3.isImm()) { in printInst()
151 int64_t imms = Op3.getImm(); in printInst()
185 if (Op2.getImm() > Op3.getImm()) { in printInst()
193 markup(O, Markup::Immediate) << "#" << Op3.getImm() + 1; in printInst()
206 markup(O, Markup::Immediate) << "#" << Op3.getImm() - Op2.getImm() + 1; in printInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp6410 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in matchAndEmitInstruction() local
6411 if (Op2.isScalarReg() && Op3.isImm()) { in matchAndEmitInstruction()
6412 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in matchAndEmitInstruction()
6432 NewOp4, Op3.getStartLoc(), Op3.getEndLoc(), getContext())); in matchAndEmitInstruction()
6433 Operands[3] = AArch64Operand::CreateImm(NewOp3, Op3.getStartLoc(), in matchAndEmitInstruction()
6434 Op3.getEndLoc(), getContext()); in matchAndEmitInstruction()
6496 AArch64Operand &Op3 = static_cast<AArch64Operand &>(*Operands[3]); in matchAndEmitInstruction() local
6499 if (Op1.isScalarReg() && Op3.isImm() && Op4.isImm()) { in matchAndEmitInstruction()
6500 const MCConstantExpr *Op3CE = dyn_cast<MCConstantExpr>(Op3.getImm()); in matchAndEmitInstruction()
6515 return Error(Op3.getStartLoc(), in matchAndEmitInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1347 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1351 Register Rt = Op3.getReg(); in expandPostRAPseudo()
1355 unsigned K3 = getKillRegState(Op3.isKill()); in expandPostRAPseudo()
1371 const MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1379 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1389 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
1393 .add(Op3); in expandPostRAPseudo()
1404 MachineOperand &Op3 = MI.getOperand(3); in expandPostRAPseudo() local
1412 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill in expandPostRAPseudo()
1425 if (Op0.getReg() != Op3.getReg()) { in expandPostRAPseudo()
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H A DHexagonSplitDouble.cpp897 MachineOperand &Op3 = MI->getOperand(3); in splitAslOr() local
898 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
899 int64_t Sh64 = Op3.getImm(); in splitAslOr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.h143 MCRegister Reg2, MCOperand Op3, SMLoc IDLoc,
H A DMipsTargetStreamer.cpp245 MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
252 TmpInst.addOperand(Op3); in emitRRRX()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp11085 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { in UpdateNodeOperands() argument
11086 SDValue Ops[] = { Op1, Op2, Op3 }; in UpdateNodeOperands()
11092 SDValue Op3, SDValue Op4) { in UpdateNodeOperands() argument
11093 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; in UpdateNodeOperands()
11099 SDValue Op3, SDValue Op4, SDValue Op5) { in UpdateNodeOperands() argument
11100 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; in UpdateNodeOperands()
11193 SDValue Op2, SDValue Op3) { in SelectNodeTo() argument
11195 SDValue Ops[] = { Op1, Op2, Op3 }; in SelectNodeTo()
11400 SDValue Op3) { in getMachineNode() argument
11402 SDValue Ops[] = { Op1, Op2, Op3 }; in getMachineNode()
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