Searched refs:Op1VT (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15368 EVT Op1VT = N->getOperand(1).getValueType(); in combineStoreFPToInt() local
15376 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) || in combineStoreFPToInt()
15377 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
15383 if ((Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) || in combineStoreFPToInt()
15390 unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; in combineStoreFPToInt()
15393 DAG.getValueType(Op1VT)}; in combineStoreFPToInt()
15858 EVT Op1VT = N->getOperand(1).getValueType(); in PerformDAGCombine() local
15878 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
15879 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15894 if (Op1VT.bitsGT(mVT)) { in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9154 EVT Op1VT = V1.getValueType(); in LowerCONCAT_VECTORS_i1() local
9156 assert(Op1VT == Op2VT && "Operand types don't match!"); in LowerCONCAT_VECTORS_i1()
9157 assert((Op1VT == MVT::v2i1 || Op1VT == MVT::v4i1 || Op1VT == MVT::v8i1) && in LowerCONCAT_VECTORS_i1()
9159 EVT VT = Op1VT.getDoubleNumVectorElementsVT(*DAG.getContext()); in LowerCONCAT_VECTORS_i1()
9161 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerCONCAT_VECTORS_i1()
9168 unsigned NumElts = 2 * Op1VT.getVectorNumElements(); in LowerCONCAT_VECTORS_i1()
9171 if (Op1VT == MVT::v4i1 || Op1VT == MVT::v8i1) { in LowerCONCAT_VECTORS_i1()
9256 EVT Op1VT = V1.getValueType(); in LowerEXTRACT_SUBVECTOR() local
9265 SDValue NewV1 = PromoteMVEPredVector(dl, V1, Op1VT, DAG); in LowerEXTRACT_SUBVECTOR()
9693 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5346 EVT Op1VT = Op1.getValueType(); in LowerMUL() local
5351 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
5353 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)), in LowerMUL()
28757 EVT Op1VT = N->getOperand(1).getValueType(); in verifyTargetSDNode() local
28758 assert(VT.isVector() && Op0VT.isVector() && Op1VT.isVector() && in verifyTargetSDNode()
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