| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 493 unsigned Ones = countTrailingOnesSlowCase(); in isMask() local
494 return (numBits == Ones) && in isMask()
495 ((Ones + countLeadingZerosSlowCase()) == BitWidth); in isMask()
504 unsigned Ones = countTrailingOnesSlowCase(); in isMask() local
505 return (Ones > 0) && ((Ones + countLeadingZerosSlowCase()) == BitWidth); in isMask()
513 unsigned Ones = countPopulationSlowCase(); in isShiftedMask() local
515 return (Ones + LeadZ + countTrailingZerosSlowCase()) == BitWidth; in isShiftedMask()
525 unsigned Ones = countPopulationSlowCase(); in isShiftedMask() local
528 if ((Ones + LeadZ + TrailZ) != BitWidth) in isShiftedMask()
530 MaskLen = Ones; in isShiftedMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 388 bool evaluateCLBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
390 bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
391 bool evaluateCTBr(const RegSubRegPair &R1, bool Zeros, bool Ones,
393 bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
1661 bool Ones, const CellMap &Inputs, in evaluateCLBr() argument
1673 evaluateCLBi(A, Zeros, Ones, CA); in evaluateCLBr()
1683 bool Ones, APInt &Result) { in evaluateCLBi() argument
1685 if (!Zeros && !Ones) in evaluateCLBi()
1690 if (Ones && (Count == 0)) in evaluateCLBi()
1697 bool Ones, const CellMap &Inputs, in evaluateCTBr() argument
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1655 SDValue Ones = DAG.getAllOnesConstant(DL, VT); in ExpandVP_SELECT() local
1656 SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Ones, EVL); in ExpandVP_SELECT()
1658 Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Ones, EVL); in ExpandVP_SELECT()
1659 Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Ones, EVL); in ExpandVP_SELECT()
1660 return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Ones, EVL); in ExpandVP_SELECT()
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| H A D | TargetLowering.cpp | 1670 APInt Ones = APInt::getAllOnes(BitWidth); in SimplifyDemandedBits() local
1671 Ones = Op0Opcode == ISD::SHL ? Ones.shl(ShiftAmt) in SimplifyDemandedBits()
1672 : Ones.lshr(ShiftAmt); in SimplifyDemandedBits()
1673 if ((DemandedBits & C->getAPIntValue()) == (DemandedBits & Ones) && in SimplifyDemandedBits()
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| H A D | DAGCombiner.cpp | 14274 SDValue Ones = SetCC.getOperand(1); in foldExtendedSignBitTest() local
14281 if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) { in foldExtendedSignBitTest()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 2093 auto Ones = MIRBuilder.buildConstant(VTy, 1); in legalizeCTPOP() local
2098 MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP}); in legalizeCTPOP()
2101 Sum = MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP}); in legalizeCTPOP()
2103 Sum = MIRBuilder.buildInstr(AArch64::G_UDOT, {Dt}, {Zeros, Ones, CTPOP}); in legalizeCTPOP()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1690 Constant *Ones = ConstantInt::getAllOnesValue(BO.getType()); in foldBinopOfSextBoolToSelect() local
1692 Value *TVal = Builder.CreateBinOp(BO.getOpcode(), Ones, C); in foldBinopOfSextBoolToSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips64InstrInfo.td | 563 // Count Ones in a Word/Doubleword
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| H A D | MipsInstrInfo.td | 1770 // Count Leading Ones/Zeros in Word
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| /freebsd/sys/contrib/dev/acpica/ |
| H A D | changes.txt | 3296 0xFFFFFFFF, the "Ones" value is now returned, which is 0xFFFFFFFFFFFFFFFF
7682 objects. 1) properly handle constants like One, Ones, Zero -- do not make
8977 using the keywords "Zero", "One", or "Ones". Lin Ming.
15031 length parameter was inadvertently changed from zero to Ones.
15083 "Ones"
15084 was not returned for the TRUE case. Changed the code to return Ones
15131 returning 1 in the TRUE case, not Ones as per the ACPI specification.
17531 Fixed a problem where the Ones opcode could get converted to a
17532 value of zero if "Ones" was used where a byte, word or dword value
17622 (Zero, One, Ones, Revision).
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| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic79xx.reg | 3320 * All Ones
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2438 uint64_t Ones = (Sum + Carry) & NonDemandedBits; in optimizeLogicalImm() local
2439 NewImm = (Imm | Ones) & Mask; in optimizeLogicalImm()
10794 SDValue Ones = DAG.getConstant(1, DL, VT8Bit); in LowerCTPOP_PARITY() local
10797 Val = DAG.getNode(AArch64ISD::UDOT, DL, DT, Zeros, Ones, Val); in LowerCTPOP_PARITY()
10800 Val = DAG.getNode(AArch64ISD::UDOT, DL, DT, Zeros, Ones, Val); in LowerCTPOP_PARITY()
10802 Val = DAG.getNode(AArch64ISD::UDOT, DL, DT, Zeros, Ones, Val); in LowerCTPOP_PARITY()
18061 SDValue Ones = N->getOperand(1); in foldVectorXorShiftIntoCmp() local
18063 !ISD::isBuildVectorAllOnes(Ones.getNode())) in foldVectorXorShiftIntoCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12177 SDValue Ones = DAG.getSplatVector(IdxVT, DL, DAG.getConstant(1, DL, XLenVT)); in lowerVECTOR_INTERLEAVE() local
12180 SDValue OddMask = DAG.getNode(ISD::AND, DL, IdxVT, StepVec, Ones); in lowerVECTOR_INTERLEAVE()
12190 SDValue Idx = DAG.getNode(ISD::SRL, DL, IdxVT, StepVec, Ones); in lowerVECTOR_INTERLEAVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 52649 SDValue Ones = N->getOperand(1); in foldVectorXorShiftIntoCmp() local
52651 !ISD::isBuildVectorAllOnes(Ones.getNode())) in foldVectorXorShiftIntoCmp()
52663 return DAG.getSetCC(SDLoc(N), VT, Shift.getOperand(0), Ones, ISD::SETGT); in foldVectorXorShiftIntoCmp()
58189 APInt Ones = APInt::getAllOnes(EltBits); in combineVectorCompare() local
58194 Results[I] = (LHSBits[I] == RHSBits[I]) ? Ones : Zero; in combineVectorCompare()
58197 Results[I] = (!AnyUndef && LHSBits[I].sgt(RHSBits[I])) ? Ones : Zero; in combineVectorCompare()
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