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Searched refs:ORI (Results 1 – 25 of 30) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchMatInt.cpp35 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
41 Insts.push_back(Inst(LoongArch::ORI, Lo12)); in generateInstSeq()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def116 FUSION_FEATURE(OriOris, hasWideImmFusion, 1, FUSION_OP_SET(ORI, ORI8),
121 FUSION_OP_SET(ORI, ORI8))
125 FUSION_OP_SET(ORI, ORI8))
H A DPPCBack2BackFusion.def155 ORI,
693 ORI,
H A DPPCExpandISEL.cpp455 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI)) in populateBlocks()
H A DPPCPreEmitPeephole.cpp438 BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR) in runOnMachineFunction()
H A DPPCInstrInfo.cpp3370 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3440 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
4016 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
4721 case PPC::ORI: in simplifyToLI()
4727 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
5337 case PPC::ORI: in isSignOrZeroExtended()
H A DPPCFrameLowering.cpp1300 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::ORI8 : PPC::ORI), TempReg) in inlineStackProbe()
1585 : PPC::ORI ); in emitEpilogue()
2575 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; in eliminateCallFramePseudoInstr()
H A DPPCAsmPrinter.cpp1693 MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0)); in emitInstruction()
1696 MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0)); in emitInstruction()
3194 MCInstBuilder(PPC::ORI).addReg(PPC::R0).addReg(PPC::R0).addImm(0)); in emitInstruction()
H A DPPCInstrInfo.td2337 def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D),
2420 def : InstAlias<"nop", (ORI R0, R0, 0)>;
3115 // Arbitrary immediate support. Implement in terms of LIS/ORI.
3117 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
3130 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
5123 dag Lo1 = (ORI (LIS 0x5555), 0x5555);
5124 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA);
5125 dag Lo2 = (ORI (LIS 0x3333), 0x3333);
5126 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC);
5127 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F);
[all …]
H A DPPCFastISel.cpp1321 Opc = PPC::ORI; in SelectBinaryIntOp()
2139 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg) in PPCMaterialize32BitInt()
H A DP10InstrResources.td917 NOP, NOP_GT_PWR6, NOP_GT_PWR7, ORI, ORI8,
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DPartialInlining.cpp184 SmallVector<OutlineRegionInfo, 4> ORI; member
502 OutliningInfo->ORI.push_back(RegInfo); in computeOutliningColdRegionsInfo()
984 OI->ORI) { in FunctionCloner()
996 ClonedOMRI->ORI.push_back(MappedRegionInfo); in FunctionCloner()
1093 if (ClonedOMRI->ORI.empty()) in doMultiRegionFunctionOutlining()
1110 ClonedOMRI->ORI) { in doMultiRegionFunctionOutlining()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h125 I_TYPE_INST(ORI);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
H A DEmulateInstructionRISCV.cpp441 {"ORI", 0x707F, 0x6013, DecodeIType<ORI>},
770 bool operator()(ORI inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchOptWInstrs.cpp212 case LoongArch::ORI: { in hasAllNBitUsers()
444 case LoongArch::ORI: in isSignExtendingOpW()
574 case LoongArch::ORI: in isSignExtendedW()
H A DLoongArchInstrInfo.cpp203 case LoongArch::ORI: in movImm()
238 case LoongArch::ORI: in isAsCheapAsAMove()
H A DLoongArchExpandPseudoInsts.cpp215 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01) in expandLoadAddressTLSLE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp230 case RISCV::ORI: { in hasAllNBitUsers()
373 case RISCV::ORI: in isSignExtendingOpW()
499 case RISCV::ORI: in isSignExtendedW()
H A DRISCVInstrInfoZb.td91 // Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.
116 // Check if (or r, imm) can be optimized to (BSETI (ORI r, i0), i1),
558 (BSETI (XLenVT (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i))),
H A DRISCVExpandPseudoInsts.cpp222 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break; in expandCCOp()
H A DRISCVInstrInfo.td659 def ORI : ALU_ri<0b110, "ori">;
1028 (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1261 def : PatGprSimm12<or, ORI>;
1896 (ORI GPR:$rs1, u32simm12:$imm)>;
2011 (ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
H A DRISCVAsmPrinter.cpp727 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols()
H A DRISCVInstrInfo.cpp1310 case RISCV::ORI: return RISCV::PseudoCCORI; break; in getPredicatedOpcode()
1540 case RISCV::ORI: in isAsCheapAsAMove()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp843 case LoongArch::ORI: in emitLAInstSeq()
921 LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_ABS_LO12)); in emitLoadAddressAbs()
1038 LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_TLS_LE_LO12)); in emitLoadAddressTLSLE()
1207 LoongArch::ORI, LoongArchMCExpr::VK_LoongArch_TLS_DESC_LO12)); in emitLoadAddressTLSDescAbs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td647 // Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands,
650 /* Disable display, so we don't override ORI */ 0>;

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