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Searched refs:OPW32 (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td1134 def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>;
1135 def SSrc_bf16: SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
1136 def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP16", 16, OperandSemantics.FP16>;
1137 def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemantics.INT>;
1138 def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_FP32", 32, OperandSemantics.FP32>;
1141 def SSrcOrLds_b32 : SrcRegOrImm9 <SRegOrLds_32, "OPW32", "OPERAND_REG_IMM_INT32", 32, OperandSemant…
1155 def SSrc_f32_Deferred : SrcRegOrImmDeferred9<SReg_32, "OPW32", "OPERAND_REG_IMM_FP32_DEFERRED", 32,…
1161 def SCSrc_b32 : SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_INLINE_C_INT32", 32, OperandSemantics.…
1169 def VSrc_b16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_INT16", 16, OperandSemantics.INT>;
1170 def VSrc_bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp290 DECODE_OPERAND_REG_7(SReg_32, OPW32) in DECODE_OPERAND_REG_8()
291 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) in DECODE_OPERAND_REG_8()
292 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) in DECODE_OPERAND_REG_8()
293 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) in DECODE_OPERAND_REG_8()
1420 case OPW32: in getVgprClassId()
1445 case OPW32: in getAgprClassId()
1471 case OPW32: in getSgprClassId()
1495 case OPW32: in getTtmpClassId()
1573 case OPW32: in decodeNonVGPRSrcOp()
1595 auto Width = llvm::AMDGPUDisassembler::OPW32; in decodeVOPDDstYOp()
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H A DAMDGPUDisassembler.h216 OPW32, enumerator
232 OPW_FIRST_ = OPW32