Lines Matching refs:OPW32
290 DECODE_OPERAND_REG_7(SReg_32, OPW32) in DECODE_OPERAND_REG_8()
291 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) in DECODE_OPERAND_REG_8()
292 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) in DECODE_OPERAND_REG_8()
293 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) in DECODE_OPERAND_REG_8()
1420 case OPW32: in getVgprClassId()
1445 case OPW32: in getAgprClassId()
1471 case OPW32: in getSgprClassId()
1495 case OPW32: in getTtmpClassId()
1573 case OPW32: in decodeNonVGPRSrcOp()
1595 auto Width = llvm::AMDGPUDisassembler::OPW32; in decodeVOPDDstYOp()
1714 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); in decodeSDWASrc32()
1731 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); in decodeSDWAVopcDst()
1737 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); in decodeSDWAVopcDst()
1745 : decodeSrcOp(OPW32, Val); in decodeBoolReg()
1749 return decodeSrcOp(OPW32, Val); in decodeSplitBarrier()