| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 365 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
375 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
377 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
379 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
380 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
381 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
384 void SelectContiguousMultiVectorLoad(SDNode *N, unsigned NumVecs,
387 void SelectDestructiveMultiIntrinsic(SDNode *N, unsigned NumVecs,
392 void SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, unsigned Opcode);
393 void SelectClamp(SDNode *N, unsigned NumVecs, unsigned Opcode);
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| H A D | AArch64ISelLowering.cpp | 15489 template <unsigned NumVecs>
15499 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
15505 EC * NumVecs); in setInfoSVEStN()
23218 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
23223 NumVecs = 2; break; in performNEONPostLDSTCombine()
23225 NumVecs = 3; break; in performNEONPostLDSTCombine()
23227 NumVecs = 4; break; in performNEONPostLDSTCombine()
23229 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
23231 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
23233 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
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| H A D | AArch64TargetTransformInfo.cpp | 4065 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
4069 for (unsigned N = 0; N < NumVecs; N++) { in getShuffleCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 215 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
223 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
231 unsigned NumVecs, const uint16_t *DOpcodes,
288 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
309 unsigned NumVecs, const uint16_t *DOpcodes,
348 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1945 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1946 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1947 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2110 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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| H A D | ARMISelLowering.cpp | 15803 unsigned NumVecs = 0; in TryCombineBaseUpdate() local
15811 NumVecs = 1; in TryCombineBaseUpdate()
15815 NumVecs = 2; in TryCombineBaseUpdate()
15819 NumVecs = 3; in TryCombineBaseUpdate()
15823 NumVecs = 4; in TryCombineBaseUpdate()
15827 NumVecs = 2; in TryCombineBaseUpdate()
15832 NumVecs = 3; in TryCombineBaseUpdate()
15837 NumVecs = 4; in TryCombineBaseUpdate()
15842 NumVecs = 2; in TryCombineBaseUpdate()
15846 NumVecs = 3; in TryCombineBaseUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 921 unsigned NumVecs) { in createInterleaveMask() argument
924 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
996 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
997 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
1003 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
1005 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
1012 if (NumVecs % 2 != 0) in concatenateVectors()
1013 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
1016 NumVecs = ResList.size(); in concatenateVectors()
1017 } while (NumVecs > 1); in concatenateVectors()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 213 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
215 bool selectVectorLoadLaneIntrinsic(unsigned Opc, unsigned NumVecs,
217 void selectVectorStoreIntrinsic(MachineInstr &I, unsigned NumVecs,
219 bool selectVectorStoreLaneIntrinsic(MachineInstr &I, unsigned NumVecs,
232 void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
5855 unsigned NumVecs, in selectVectorLoadIntrinsic() argument
5859 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadIntrinsic()
5872 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadIntrinsic()
5884 unsigned Opc, unsigned NumVecs, MachineInstr &I) { in selectVectorLoadLaneIntrinsic() argument
5887 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadLaneIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 379 llvm::SmallVector<int, 16> createInterleaveMask(unsigned VF, unsigned NumVecs);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10974 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10977 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
10981 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
10984 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
11557 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
11558 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
11603 unsigned NumVecs = 2; in LowerVectorStore() local
11614 NumVecs = 4; in LowerVectorStore()
11616 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorStore()
11617 unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; in LowerVectorStore()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 17860 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
17863 NumVecs = 4; in EmitPPCBuiltinExpr()
17872 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()
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