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Searched refs:NumRegs (Results 1 – 25 of 73) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DAVR.cpp58 ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegs) const { in classifyArgumentType()
62 if (TySize == 8 && NumRegs >= 2) { in classifyArgumentType()
63 NumRegs -= 2; in classifyArgumentType()
73 if (TySize <= NumRegs * 8) { in classifyArgumentType()
74 NumRegs -= TySize / 8; in classifyArgumentType()
85 NumRegs = 0; in classifyArgumentType()
102 unsigned NumRegs = ParamRegs; in computeInfo() local
104 NumRegs = 0; in computeInfo()
106 NumRegs -= 2; in computeInfo()
108 I.info = classifyArgumentType(I.type, NumRegs); in computeInfo()
H A DAMDGPU.cpp62 uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32; in isHomogeneousAggregateSmallEnough() local
65 return Members * NumRegs <= MaxNumRegsForArgsRet; in isHomogeneousAggregateSmallEnough()
70 unsigned NumRegs = 0; in numRegsForType() local
92 NumRegs += numRegsForType(FieldTy); in numRegsForType()
95 return NumRegs; in numRegsForType()
248 unsigned NumRegs = (Size + 31) / 32; in classifyArgumentType() local
249 NumRegsLeft -= std::min(NumRegsLeft, NumRegs); in classifyArgumentType()
263 unsigned NumRegs = numRegsForType(Ty); in classifyArgumentType() local
264 if (NumRegsLeft >= NumRegs) { in classifyArgumentType()
265 NumRegsLeft -= NumRegs; in classifyArgumentType()
[all …]
H A DPPC.cpp471 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs"); in EmitVAArg() local
475 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1)); in EmitVAArg()
476 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U)); in EmitVAArg()
480 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond"); in EmitVAArg()
512 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
519 NumRegs = in EmitVAArg()
520 Builder.CreateAdd(NumRegs, in EmitVAArg()
522 Builder.CreateStore(NumRegs, NumRegsAddr); in EmitVAArg()
813 uint32_t NumRegs = in isHomogeneousAggregateSmallEnough() local
820 return Members * NumRegs <= 8; in isHomogeneousAggregateSmallEnough()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp131 unsigned NumRegs = RC->getNumRegs(); in compute() local
134 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
163 RCI.NumRegs = N + CSRAlias.size(); in compute()
164 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
176 if (StressRA && RCI.NumRegs > StressRA) in compute()
177 RCI.NumRegs = StressRA; in compute()
182 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
190 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
H A DLiveVariables.cpp440 void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) { in HandleRegMask() argument
444 for (unsigned Reg = 1; Reg != NumRegs; ++Reg) { in HandleRegMask()
455 if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) && in HandleRegMask()
514 unsigned NumRegs) { in runOnInstr() argument
563 HandleRegMask(MI.getOperand(Mask), NumRegs); in runOnInstr()
575 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) { in runOnBlock() argument
592 runOnInstr(MI, Defs, NumRegs); in runOnBlock()
623 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
633 const unsigned NumRegs = TRI->getNumSupportedRegs(mf); in analyze() local
634 PhysRegDef.assign(NumRegs, nullptr); in analyze()
[all …]
H A DExecutionDomainFix.cpp71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
92 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
160 LiveRegs.assign(NumRegs, nullptr); in enterBasicBlock()
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
H A DCFIInstrInserter.cpp154 unsigned NumRegs = TRI.getNumSupportedRegs(MF); in calculateCFAInfo() local
164 MBBInfo.IncomingCSRSaved.resize(NumRegs); in calculateCFAInfo()
165 MBBInfo.OutgoingCSRSaved.resize(NumRegs); in calculateCFAInfo()
184 unsigned NumRegs = TRI.getNumSupportedRegs(*MF); in calculateOutgoingCFAInfo() local
185 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); in calculateOutgoingCFAInfo()
H A DRDFRegisters.cpp144 unsigned NumRegs = TRI.getNumRegs(); in getUnits()
146 for (unsigned I = 0, E = (NumRegs + 31) / 32; I != E; ++I) { in getUnits()
150 if (I + 1 == E && NumRegs % 32 != 0) // Last word may be partial in getUnits()
151 C &= maskTrailingOnes<unsigned>(NumRegs % 32); in getUnits() local
H A DVirtRegMap.cpp79 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); in grow() local
80 Virt2PhysMap.resize(NumRegs); in grow()
81 Virt2StackSlotMap.resize(NumRegs); in grow()
82 Virt2SplitMap.resize(NumRegs); in grow()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp88 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
111 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
113 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
117 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
121 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
127 bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
128 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
144 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
146 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
148 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp108 unsigned NumRegs = 1; in getRegistersForValue() local
110 NumRegs = in getRegistersForValue()
129 for (; NumRegs; --NumRegs, ++I) { in getRegistersForValue()
499 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
501 assert(NumRegs == SourceRegs.size() && in lowerInlineAsm()
505 if (NumRegs > 1) { in lowerInlineAsm()
511 InlineAsm::Flag Flag(InlineAsm::Kind::RegUse, NumRegs); in lowerInlineAsm()
526 const unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
527 if (NumRegs > 0) { in lowerInlineAsm()
528 unsigned Flag = InlineAsm::Flag(InlineAsm::Kind::Clobber, NumRegs); in lowerInlineAsm()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h32 unsigned NumRegs = 0; member
41 return ArrayRef(Order.get(), NumRegs);
95 return get(RC).NumRegs; in getNumAllocatableRegs()
H A DExecutionDomainFix.h125 const unsigned NumRegs; variable
140 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {} in ExecutionDomainFix()
H A DLiveVariables.h179 unsigned NumRegs);
181 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp65 unsigned NumRegs) in RegisterFile() argument
69 initialize(SM, NumRegs);
72 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize() argument
77 RegisterFiles.emplace_back(NumRegs); in initialize()
674 unsigned NumRegs = NumPhysRegs[I]; in isAvailable() local
675 if (!NumRegs) in isAvailable()
685 if (RMT.NumPhysRegs < NumRegs) { in isAvailable()
698 NumRegs = RMT.NumPhysRegs; in isAvailable()
701 if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs)) in isAvailable()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h161 unsigned NumRegs; // Number of entries in the array variable
281 NumRegs = NR; in InitMCRegisterInfo()
306 RegAliasesCache.resize(NumRegs); in InitMCRegisterInfo()
362 assert(RegNo < NumRegs &&
400 return NumRegs; in getNumRegs()
462 assert(RegNo < NumRegs && in getEncodingValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp230 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; in EmitTargetCodeForMemcpy() local
233 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
237 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
238 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
233 unsigned NumRegs = 0);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.h739 unsigned NumRegs;
822 SlotNo += NumRegs;
832 SlotNo += NumRegs;
838 assert(ID >= NumRegs);
839 ID -= NumRegs;
847 assert(ID >= NumRegs);
848 ID -= NumRegs;
895 LocIDToLocIdx.resize(NumRegs, LocIdx::MakeIllegalLoc());
986 bool isSpill(LocIdx Idx) const { return LocIdxToLocID[Idx] >= NumRegs; }
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp50 unsigned NumRegs = TLI.getNumRegisters(Ctx, VT); in computeLegalValueVTs() local
52 for (unsigned I = 0; I != NumRegs; ++I) in computeLegalValueVTs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1629 unsigned NumRegs = 0; in printMatrixTileList()
1632 ++NumRegs; in printMatrixTileList()
1641 if (Printed + 1 != NumRegs) in printVectorList()
1658 unsigned NumRegs = 1; in printVectorList()
1664 NumRegs = 2; in printVectorList()
1668 NumRegs = 3; in printVectorList()
1673 NumRegs = 4; in printVectorList()
1701 NumRegs > 1 && Stride == 1 && in printVectorList()
1704 Reg < getNextVectorRegister(Reg, NumRegs - 1)) { in printVectorList()
1707 if (NumRegs > in printVectorList()
1616 unsigned NumRegs = 0; printMatrixTileList() local
1645 unsigned NumRegs = 1; printVectorList() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp210 const unsigned NumRegs = Flag.getNumOperandRegisters(); in tryInlineAsm() local
211 if (NumRegs) in tryInlineAsm()
228 || NumRegs != 2) in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td1063 class PPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
1064 let Name = "SVEPredicateList" # NumRegs # "x" # ElementWidth;
1067 # NumRegs #", 0, "#ElementWidth #">";
1069 # NumRegs #">";
1093 class PPRVectorListMul<int ElementWidth, int NumRegs> : PPRVectorList<ElementWidth, NumRegs> {
1094 let Name = "SVEPredicateListMul" # NumRegs # "x" # ElementWidth;
1097 "isTypedVectorListMultiple<RegKind::SVEPredicateVector, " # NumRegs # ", 0, "
1230 class ZPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
1231 let Name = "SVEVectorList" # NumRegs # ElementWidth;
1234 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp165 const unsigned NumRegs = Flag.getNumOperandRegisters(); in selectInlineAsm() local
166 if (NumRegs) in selectInlineAsm()
194 NumRegs != 2) in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp244 static const unsigned NumRegs = std::size(RegList); in CC_X86_32_MCUInReg()
279 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree); in CC_X86_32_MCUInReg()
243 static const unsigned NumRegs = std::size(RegList); CC_X86_32_MCUInReg() local

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