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Searched refs:NumRegs (Results 1 – 25 of 80) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DAVR.cpp58 ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegs) const { in classifyArgumentType()
62 if (TySize == 8 && NumRegs >= 2 && Ty->isIntegralOrEnumerationType()) { in classifyArgumentType()
63 NumRegs -= 2; in classifyArgumentType()
73 if (TySize <= NumRegs * 8) { in classifyArgumentType()
74 NumRegs -= TySize / 8; in classifyArgumentType()
85 NumRegs = 0; in classifyArgumentType()
102 unsigned NumRegs = ParamRegs; in computeInfo() local
104 NumRegs = 0; in computeInfo()
106 NumRegs -= 2; in computeInfo()
108 I.info = classifyArgumentType(I.type, NumRegs); in computeInfo()
H A DAMDGPU.cpp74 uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32; in isHomogeneousAggregateSmallEnough() local
77 return Members * NumRegs <= MaxNumRegsForArgsRet; in isHomogeneousAggregateSmallEnough()
82 unsigned NumRegs = 0; in numRegsForType() local
104 NumRegs += numRegsForType(FieldTy); in numRegsForType()
107 return NumRegs; in numRegsForType()
257 unsigned NumRegs = (Size + 31) / 32; in classifyArgumentType() local
258 NumRegsLeft -= std::min(NumRegsLeft, NumRegs); in classifyArgumentType()
272 unsigned NumRegs = numRegsForType(Ty); in classifyArgumentType() local
273 if (NumRegsLeft >= NumRegs) { in classifyArgumentType()
274 NumRegsLeft -= NumRegs; in classifyArgumentType()
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H A DPPC.cpp475 llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs"); in EmitVAArg() local
479 NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1)); in EmitVAArg()
480 NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U)); in EmitVAArg()
484 Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond"); in EmitVAArg()
516 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity())); in EmitVAArg()
523 NumRegs = in EmitVAArg()
524 Builder.CreateAdd(NumRegs, in EmitVAArg()
526 Builder.CreateStore(NumRegs, NumRegsAddr); in EmitVAArg()
817 uint32_t NumRegs = in isHomogeneousAggregateSmallEnough() local
824 return Members * NumRegs <= 8; in isHomogeneousAggregateSmallEnough()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp134 unsigned NumRegs = RC->getNumRegs(); in compute() local
137 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
171 RCI.NumRegs = N + CSRAlias.size(); in compute()
172 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); in compute()
184 if (StressRA && RCI.NumRegs > StressRA) in compute()
185 RCI.NumRegs = StressRA; in compute()
190 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) in compute()
198 for (unsigned I = 0; I != RCI.NumRegs; ++I) in compute()
H A DLiveVariables.cpp436 void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) { in HandleRegMask() argument
440 for (unsigned Reg = 1; Reg != NumRegs; ++Reg) { in HandleRegMask()
451 if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) && in HandleRegMask()
507 unsigned NumRegs) { in runOnInstr() argument
556 HandleRegMask(MI.getOperand(Mask), NumRegs); in runOnInstr()
568 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) { in runOnBlock() argument
585 runOnInstr(MI, Defs, NumRegs); in runOnBlock()
616 for (unsigned i = 0; i != NumRegs; ++i) in runOnBlock()
626 const unsigned NumRegs = TRI->getNumSupportedRegs(mf); in analyze() local
627 PhysRegDef.assign(NumRegs, nullptr); in analyze()
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H A DExecutionDomainFix.cpp71 assert(unsigned(rx) < NumRegs && "Invalid index"); in setLiveReg()
82 assert(unsigned(rx) < NumRegs && "Invalid index"); in kill()
92 assert(unsigned(rx) < NumRegs && "Invalid index"); in force()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse()
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge()
160 LiveRegs.assign(NumRegs, nullptr); in enterBasicBlock()
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock()
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); in runOnMachineFunction()
H A DCFIInstrInserter.cpp155 unsigned NumRegs = TRI.getNumSupportedRegs(MF); in calculateCFAInfo() local
165 MBBInfo.IncomingCSRSaved.resize(NumRegs); in calculateCFAInfo()
166 MBBInfo.OutgoingCSRSaved.resize(NumRegs); in calculateCFAInfo()
185 unsigned NumRegs = TRI.getNumSupportedRegs(*MF); in calculateOutgoingCFAInfo() local
186 BitVector CSRSaved(NumRegs), CSRRestored(NumRegs); in calculateOutgoingCFAInfo()
H A DRDFRegisters.cpp144 unsigned NumRegs = TRI.getNumRegs(); in getUnits() local
146 for (unsigned I = 0, E = (NumRegs + 31) / 32; I != E; ++I) { in getUnits()
150 if (I + 1 == E && NumRegs % 32 != 0) // Last word may be partial in getUnits()
151 C &= maskTrailingOnes<unsigned>(NumRegs % 32); in getUnits()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp75 bool canAssign(unsigned StartReg, unsigned NumRegs) const;
117 unsigned NumRegs = Intervals.size(); in tryAssignRegisters() local
119 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
123 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
127 for (unsigned N = 0; N < NumRegs; ++N) in tryAssignRegisters()
133 bool GCNNSAReassignImpl::canAssign(unsigned StartReg, unsigned NumRegs) const { in canAssign()
134 for (unsigned N = 0; N < NumRegs; ++N) { in canAssign()
150 unsigned NumRegs = Intervals.size(); in scavengeRegs() local
152 if (NumRegs > MaxNumVGPRs) in scavengeRegs()
154 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
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H A DSILowerSGPRSpills.cpp358 unsigned NumRegs = MaxNumVGPRsForWwmAllocation; in determineRegsForWWMAllocation() local
359 NumRegs = in determineRegsForWWMAllocation()
360 std::min(static_cast<unsigned>(MFI->getSGPRSpillVGPRs().size()), NumRegs); in determineRegsForWWMAllocation()
367 (I < NumRegs) && (Reg >= AMDGPU::VGPR0); --Reg) { in determineRegsForWWMAllocation()
375 if (I != NumRegs) { in determineRegsForWWMAllocation()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h649 inline static unsigned encodeRegListNumRegs(unsigned NumRegs) { in encodeRegListNumRegs() argument
650 assert(NumRegs > 0 && NumRegs < 14 && NumRegs != 12 && in encodeRegListNumRegs()
652 if (NumRegs == 13) in encodeRegListNumRegs()
655 return RLISTENCODE::RA + (NumRegs - 1); in encodeRegListNumRegs()
661 unsigned NumRegs = (RlistVal - RLISTENCODE::RA) + 1; in getStackAdjBase() local
664 ++NumRegs; in getStackAdjBase()
667 return alignTo(NumRegs * RegSize, 16); in getStackAdjBase()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp108 unsigned NumRegs = 1; in getRegistersForValue() local
110 NumRegs = in getRegistersForValue()
129 for (; NumRegs; --NumRegs, ++I) { in getRegistersForValue()
499 unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
501 assert(NumRegs == SourceRegs.size() && in lowerInlineAsm()
505 if (NumRegs > 1) { in lowerInlineAsm()
511 InlineAsm::Flag Flag(InlineAsm::Kind::RegUse, NumRegs); in lowerInlineAsm()
526 const unsigned NumRegs = OpInfo.Regs.size(); in lowerInlineAsm() local
527 if (NumRegs > 0) { in lowerInlineAsm()
528 unsigned Flag = InlineAsm::Flag(InlineAsm::Kind::Clobber, NumRegs); in lowerInlineAsm()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h33 unsigned NumRegs = 0; member
42 return ArrayRef(Order.get(), NumRegs);
100 return get(RC).NumRegs; in getNumAllocatableRegs()
H A DExecutionDomainFix.h125 const unsigned NumRegs; variable
140 : MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {} in ExecutionDomainFix()
H A DLiveVariables.h180 unsigned NumRegs);
182 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetTransformInfo.cpp24 unsigned C1NumRegs = C1.NumRegs + (C1.NumBaseAdds != 0); in isLSRCostLess()
25 unsigned C2NumRegs = C2.NumRegs + (C2.NumBaseAdds != 0); in isLSRCostLess()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp70 unsigned NumRegs) in RegisterFile() argument
74 initialize(SM, NumRegs);
77 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) { in initialize() argument
82 RegisterFiles.emplace_back(NumRegs); in initialize()
682 unsigned NumRegs = NumPhysRegs[I]; in isAvailable() local
683 if (!NumRegs) in isAvailable()
693 if (RMT.NumPhysRegs < NumRegs) { in isAvailable()
706 NumRegs = RMT.NumPhysRegs; in isAvailable()
709 if (RMT.NumPhysRegs < (RMT.NumUsedPhysRegs + NumRegs)) in isAvailable()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp243 static const unsigned NumRegs = std::size(RegList); in CC_X86_32_MCUInReg() local
278 bool UseRegs = PendingMembers.size() <= std::min(2U, NumRegs - FirstFree); in CC_X86_32_MCUInReg()
357 unsigned NumRegs = PendingMembers.size(); in CC_X86_64_I128() local
358 assert(NumRegs == 2 && "Should have two parts"); in CC_X86_64_I128()
362 ArrayRef<MCPhysReg> Allocated = State.AllocateRegBlock(Regs, NumRegs); in CC_X86_64_I128()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h165 unsigned NumRegs; // Number of entries in the array variable
287 NumRegs = NR; in InitMCRegisterInfo()
312 RegAliasesCache.resize(NumRegs); in InitMCRegisterInfo()
368 assert(Reg.id() < NumRegs &&
416 return NumRegs; in getNumRegs()
478 assert(Reg.id() < NumRegs && in getEncodingValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp235 unsigned NumRegs = NextEmittedNumMemOps - EmittedNumMemOps; in EmitTargetCodeForMemcpy() local
238 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
242 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
243 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h229 void initialize(const MCSchedModel &SM, unsigned NumRegs);
233 unsigned NumRegs = 0);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.h734 unsigned NumRegs;
818 SlotNo += NumRegs;
828 SlotNo += NumRegs;
834 assert(ID >= NumRegs);
835 ID -= NumRegs;
843 assert(ID >= NumRegs);
844 ID -= NumRegs;
891 LocIDToLocIdx.resize(NumRegs, LocIdx::MakeIllegalLoc());
983 bool isSpill(LocIdx Idx) const { return LocIdxToLocID[Idx] >= NumRegs; }
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp49 unsigned NumRegs = TLI.getNumRegisters(Ctx, VT); in computeLegalValueVTs() local
51 for (unsigned I = 0; I != NumRegs; ++I) in computeLegalValueVTs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp208 const unsigned NumRegs = Flag.getNumOperandRegisters(); in tryInlineAsm() local
209 if (NumRegs) in tryInlineAsm()
226 || NumRegs != 2) in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1642 unsigned NumRegs = 0; in printMatrixTileList() local
1645 ++NumRegs; in printMatrixTileList()
1654 if (Printed + 1 != NumRegs) in printMatrixTileList()
1671 unsigned NumRegs = 1; in printVectorList() local
1677 NumRegs = 2; in printVectorList()
1681 NumRegs = 3; in printVectorList()
1686 NumRegs = 4; in printVectorList()
1714 NumRegs > 1 && Stride == 1 && in printVectorList()
1717 Reg < getNextVectorRegister(Reg, NumRegs - 1)) { in printVectorList()
1720 if (NumRegs > 1) { in printVectorList()
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