| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1201 SDValue N00 = N0.getOperand(0); in reassociateOpsCommutative() local
1213 return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags); in reassociateOpsCommutative()
1219 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags); in reassociateOpsCommutative()
1230 if (N1 == N00 || N1 == N01) in reassociateOpsCommutative()
1235 if (N1 == N00) in reassociateOpsCommutative()
1239 return N00; in reassociateOpsCommutative()
1245 if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) { in reassociateOpsCommutative()
1253 if (N1 != N00) { in reassociateOpsCommutative()
1258 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00})) in reassociateOpsCommutative()
1259 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00); in reassociateOpsCommutative()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44002 SDValue N00 = N0.getOperand(0); in combineBitcast() local
44003 SDLoc dl(N00); in combineBitcast()
44004 N00 = LowUndef ? DAG.getAnyExtOrTrunc(N00, dl, MVT::i32) in combineBitcast()
44005 : DAG.getZExtOrTrunc(N00, dl, MVT::i32); in combineBitcast()
44006 return DAG.getNode(X86ISD::MMX_MOVW2D, dl, VT, N00); in combineBitcast()
44022 SDValue N00 = N0.getOperand(0); in combineBitcast() local
44023 if (N00.getValueType().is128BitVector()) in combineBitcast()
44024 return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT, in combineBitcast()
44025 DAG.getBitcast(MVT::v2i64, N00)); in combineBitcast()
45382 SDValue N00 = N0.getOperand(0); in combineToExtendBoolVectorInReg() local
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| H A D | X86ISelDAGToDAG.cpp | 1523 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend() local
1524 if (!N00.isMachineOpcode() || N00.getMachineOpcode() != ExpectedOpc) in tryOptimizeRem8Extend()
1531 MVT::i64, N00); in tryOptimizeRem8Extend()
1535 ReplaceUses(N, N00.getNode()); in tryOptimizeRem8Extend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9691 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local
9696 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
12680 SDValue N00 = N0.getOperand(0); in AddCombineVUZPToVPADDL() local
12684 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || in AddCombineVUZPToVPADDL()
12685 N00 == N10) in AddCombineVUZPToVPADDL()
12690 if (!N00.getValueType().is64BitVector() || in AddCombineVUZPToVPADDL()
12709 EVT ElemTy = N00.getValueType().getVectorElementType(); in AddCombineVUZPToVPADDL()
12713 N00.getOperand(0), N00.getOperand(1)); in AddCombineVUZPToVPADDL()
14142 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local
14145 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 3490 SDValue N00 = N0.getOperand(0); in doPeepholeSExtW() local
3500 N00, N01); in doPeepholeSExtW()
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| H A D | RISCVISelLowering.cpp | 13580 SDValue N00 = N0.getOperand(0); in combineDeMorganOfBoolean()
13585 if (!DAG.MaskedValueIsZero(N00, Mask) || !DAG.MaskedValueIsZero(N10, Mask)) in combineDeMorganOfBoolean()
13591 SDValue Logic = DAG.getNode(Opc, DL, VT, N00, N10);
13842 SDValue N00 = N0.getOperand(0); in performXORCombine()
13844 SDValue LHS = N00.getOperand(0); in performXORCombine()
13845 SDValue RHS = N00.getOperand(1); in performXORCombine()
13846 SDValue CC = N00.getOperand(2); in performXORCombine()
13849 SDValue Setcc = DAG.getSetCC(SDLoc(N00), N0.getOperand(0).getValueType(), in performXORCombine()
16508 SDValue N00 = N0.getOperand(0); in combineTruncOfSraSext()
16510 if (!N00 in combineTruncOfSraSext()
13577 SDValue N00 = N0.getOperand(0); combineDeMorganOfBoolean() local
13839 SDValue N00 = N0.getOperand(0); performXORCombine() local
16505 SDValue N00 = N0.getOperand(0); combineTruncOfSraSext() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5344 SDValue N00 = skipExtensionForVectorMULL(N0.getOperand(0), DAG); in LowerMUL() local
5351 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
19267 SDValue N00 = N0->getOperand(IsStrict ? 1 : 0); in performExtractVectorEltCombine() local
19271 SDValue Other = N00; in performExtractVectorEltCombine()
19275 Shuffle = dyn_cast<ShuffleVectorSDNode>(N00); in performExtractVectorEltCombine()
19328 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
19330 EVT N00VT = N00.getValueType(); in performConcatVectorsCombine()
19342 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
19400 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
19402 if (isBitwiseVectorNegate(N00) && N0->isOnlyUserOf(N00.getNode()) && in performConcatVectorsCombine()
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