| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1221 SDValue N00 = N0.getOperand(0); in reassociateOpsCommutative() local
1235 return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags); in reassociateOpsCommutative()
1242 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags); in reassociateOpsCommutative()
1253 if (N1 == N00 || N1 == N01) in reassociateOpsCommutative()
1258 if (N1 == N00) in reassociateOpsCommutative()
1262 return N00; in reassociateOpsCommutative()
1268 if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) { in reassociateOpsCommutative()
1276 if (N1 != N00) { in reassociateOpsCommutative()
1281 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00})) in reassociateOpsCommutative()
1282 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00); in reassociateOpsCommutative()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 45848 SDValue N00 = N0.getOperand(0); in combineBitcast() local
45849 SDLoc dl(N00); in combineBitcast()
45850 N00 = LowUndef ? DAG.getAnyExtOrTrunc(N00, dl, MVT::i32) in combineBitcast()
45851 : DAG.getZExtOrTrunc(N00, dl, MVT::i32); in combineBitcast()
45852 return DAG.getNode(X86ISD::MMX_MOVW2D, dl, VT, N00); in combineBitcast()
45868 SDValue N00 = N0.getOperand(0); in combineBitcast() local
45869 if (N00.getValueType().is128BitVector()) in combineBitcast()
45870 return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT, in combineBitcast()
45871 DAG.getBitcast(MVT::v2i64, N00)); in combineBitcast()
47224 SDValue N00 = N0.getOperand(0); in combineToExtendBoolVectorInReg() local
[all …]
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| H A D | X86ISelDAGToDAG.cpp | 1567 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend() local
1568 if (!N00.isMachineOpcode() || N00.getMachineOpcode() != ExpectedOpc) in tryOptimizeRem8Extend()
1575 MVT::i64, N00); in tryOptimizeRem8Extend()
1579 ReplaceUses(N, N00.getNode()); in tryOptimizeRem8Extend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9743 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local
9748 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
12747 SDValue N00 = N0.getOperand(0); in AddCombineVUZPToVPADDL() local
12751 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || in AddCombineVUZPToVPADDL()
12752 N00 == N10) in AddCombineVUZPToVPADDL()
12757 if (!N00.getValueType().is64BitVector() || in AddCombineVUZPToVPADDL()
12776 EVT ElemTy = N00.getValueType().getVectorElementType(); in AddCombineVUZPToVPADDL()
12780 N00.getOperand(0), N00.getOperand(1)); in AddCombineVUZPToVPADDL()
14219 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local
14222 DAG.getNode(ISD::MUL, DL, VT, N00, N1), in PerformVMULCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5495 SDValue N00 = skipExtensionForVectorMULL(N0.getOperand(0), DAG); in LowerMUL() local
5502 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
19939 SDValue N00 = N0->getOperand(IsStrict ? 1 : 0); in performExtractVectorEltCombine() local
19943 SDValue Other = N00; in performExtractVectorEltCombine()
19947 Shuffle = dyn_cast<ShuffleVectorSDNode>(N00); in performExtractVectorEltCombine()
19989 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
19991 EVT N00VT = N00.getValueType(); in performConcatVectorsCombine()
19992 unsigned N00Opc = N00.getOpcode(), N10Opc = N10.getOpcode(); in performConcatVectorsCombine()
20015 DAG.getNode(ISD::BITCAST, DL, MidVT, N00), in performConcatVectorsCombine()
20033 N00->getOperand(1) == N10->getOperand(1)) { in performConcatVectorsCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 4037 SDValue N00 = N0.getOperand(0); in doPeepholeSExtW() local
4047 N00, N01); in doPeepholeSExtW()
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| H A D | RISCVISelLowering.cpp | 15570 SDValue N00 = N0.getOperand(0); in combineDeMorganOfBoolean() local
15575 if (!DAG.MaskedValueIsZero(N00, Mask) || !DAG.MaskedValueIsZero(N10, Mask)) in combineDeMorganOfBoolean()
15581 SDValue Logic = DAG.getNode(Opc, DL, VT, N00, N10); in combineDeMorganOfBoolean()
19360 SDValue N00 = N0.getOperand(0); in combineTruncOfSraSext() local
19362 if (!N00.getValueType().isVector() || in combineTruncOfSraSext()
19363 N00.getValueType() != N10.getValueType() || in combineTruncOfSraSext()
19371 return DAG.getNode(ISD::SRA, SDLoc(N), N->getValueType(0), N00, SMin); in combineTruncOfSraSext()
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| /freebsd/share/misc/ |
| H A D | pci_vendors | 26874 8061 NX E310-01N00 Ethernet Controller
26875 8062 NX E310-01N00 Ethernet Controller Virtual Function
26890 8080 NX E311-01N00 Ethernet Controller
26891 8081 NX E311-01N00 Ethernet Controller Virtual Function
26901 80a0 NX E312-01N00 Ethernet Controller
26902 80a1 NX E312-01N00 Ethernet Controller Virtual Function
26908 80b6 NX E310S-01N00 Ethernet Controller
26909 80b7 NX E310S-01N00 Ethernet Controller Virtual Function
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