44002         SDValue N00 = N0.getOperand(0);  in combineBitcast()  local
44003         SDLoc dl(N00);  in combineBitcast()
44004         N00 = LowUndef ? DAG.getAnyExtOrTrunc(N00, dl, MVT::i32)  in combineBitcast()
44005                        : DAG.getZExtOrTrunc(N00, dl, MVT::i32);  in combineBitcast()
44006         return DAG.getNode(X86ISD::MMX_MOVW2D, dl, VT, N00);  in combineBitcast()
44022       SDValue N00 = N0.getOperand(0);  in combineBitcast()  local
44023       if (N00.getValueType().is128BitVector())  in combineBitcast()
44024         return DAG.getNode(X86ISD::MOVDQ2Q, SDLoc(N00), VT,  in combineBitcast()
44025                            DAG.getBitcast(MVT::v2i64, N00));  in combineBitcast()
45382   SDValue N00 = N0.getOperand(0);  in combineToExtendBoolVectorInReg()  local
45383   EVT SclVT = N00.getValueType();  in combineToExtendBoolVectorInReg()
45401     Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);  in combineToExtendBoolVectorInReg()
45417     Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);  in combineToExtendBoolVectorInReg()
45425     SDValue Scl = DAG.getAnyExtOrTrunc(N00, DL, SVT);  in combineToExtendBoolVectorInReg()
48116     SDValue N00 = N0.getOperand(1);  in combineShiftLeft()  local
48122       return DAG.getNode(X86ISD::VSHLV, DL, VT, N00, N1);  in combineShiftLeft()
48125     if (ISD::isConstantSplatVectorAllZeros(N00.getNode()) &&  in combineShiftLeft()
48137     SDValue N00 = N0.getOperand(0);  in combineShiftLeft()  local
48152     if (N00.getOpcode() == X86ISD::SETCC_CARRY) {  in combineShiftLeft()
48154     } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&  in combineShiftLeft()
48155                N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {  in combineShiftLeft()
48157     } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||  in combineShiftLeft()
48158                 N00.getOpcode() == ISD::ANY_EXTEND) &&  in combineShiftLeft()
48159                N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {  in combineShiftLeft()
48160       MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());  in combineShiftLeft()
48163       return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));  in combineShiftLeft()
48208   SDValue N00 = N0.getOperand(0);  in combineShiftRightArithmetic()  local
48225         DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));  in combineShiftRightArithmetic()
48255     SDValue N00 = N0.getOperand(1);  in combineShiftRightLogical()  local
48261       return DAG.getNode(X86ISD::VSRLV, DL, VT, N00, N1);  in combineShiftRightLogical()
48264     if (ISD::isConstantSplatVectorAllZeros(N00.getNode()) &&  in combineShiftRightLogical()
49215   SDValue N00 = N0.getOperand(0);  in convertIntLogicToFPLogic()  local
49217   EVT N00Type = N00.getValueType();  in convertIntLogicToFPLogic()
49228     SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);  in convertIntLogicToFPLogic()
49255   SDValue Vec00 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, N00);  in convertIntLogicToFPLogic()
50410   SDValue N00 = N0->getOperand(0);  in foldMaskedMerge()  local
50414   if (SDValue Result = foldMaskedMergeImpl(N00, N01, N10, N11, DL, DAG))  in foldMaskedMerge()
50416   if (SDValue Result = foldMaskedMergeImpl(N01, N00, N10, N11, DL, DAG))  in foldMaskedMerge()
50418   if (SDValue Result = foldMaskedMergeImpl(N10, N11, N00, N01, DL, DAG))  in foldMaskedMerge()
50420   if (SDValue Result = foldMaskedMergeImpl(N11, N10, N00, N01, DL, DAG))  in foldMaskedMerge()
52505   SDValue N00 = N0.getOperand(0);  in detectPMADDUBSW()  local
52513     std::swap(N00, N01);  in detectPMADDUBSW()
52518   if (N00.getOpcode() != ISD::ZERO_EXTEND ||  in detectPMADDUBSW()
52525   N00 = N00.getOperand(0);  in detectPMADDUBSW()
52531   if (N00.getValueType().getVectorElementType() != MVT::i8 ||  in detectPMADDUBSW()
52538   if (N00.getOpcode() != ISD::BUILD_VECTOR ||  in detectPMADDUBSW()
52554     SDValue N00Elt = N00.getOperand(i);  in detectPMADDUBSW()
53717     SDValue N00 = N0.getOperand(0);  in combineSignExtendInReg()  local
53721     if (N00.getOpcode() == ISD::LOAD && Subtarget.hasInt256())  in combineSignExtendInReg()
53722       if (!ISD::isNormalLoad(N00.getNode()))  in combineSignExtendInReg()
53730     if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {  in combineSignExtendInReg()
53732           DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, N00, N1);  in combineSignExtendInReg()
54174     SDValue N00 = N0.getOperand(0);  in combineZext()  local
54176     unsigned NumSrcEltBits = N00.getScalarValueSizeInBits();  in combineZext()
54178     if ((N00.isUndef() || DAG.MaskedValueIsZero(N00, ZeroMask)) &&  in combineZext()
54180       return concatSubVectors(N00, N01, DAG, dl);  in combineZext()
55540   SDValue N00 = N0.getOperand(0);  in matchPMADDWD_2()  local
55547   if (N00.getOpcode() != ISD::SIGN_EXTEND ||  in matchPMADDWD_2()
55554   N00 = N00.getOperand(0);  in matchPMADDWD_2()
55560   EVT InVT = N00.getValueType();  in matchPMADDWD_2()
55566   if (N00.getOpcode() != ISD::BUILD_VECTOR ||  in matchPMADDWD_2()
55579   for (unsigned i = 0; i != N00.getNumOperands(); ++i) {  in matchPMADDWD_2()
55580     SDValue N00Elt = N00.getOperand(i);  in matchPMADDWD_2()