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Searched refs:MovOpc (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp900 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
908 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
909 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
917 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams() local
920 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); in EmitSwapFPIntParams()
923 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE); in EmitSwapFPIntParams()
926 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); in EmitSwapFPIntParams()
927 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
930 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
933 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
[all …]
H A DMipsSEInstrInfo.h114 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
H A DMipsAsmPrinter.h102 void EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc,
H A DMipsSEInstrInfo.cpp729 unsigned CvtOpc, unsigned MovOpc, in expandCvtFPInt() argument
731 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); in expandCvtFPInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp42 unsigned MovOpc; member in __anon03252fca0111::SILateBranchLowering
178 auto SetExec = BuildMI(*MI.getParent(), MI, DL, TII->get(MovOpc), ExecReg); in expandChainCall()
221 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in run()
272 BuildMI(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII->get(MovOpc), in run()
H A DSIRegisterInfo.cpp115 unsigned MovOpc; member
137 MovOpc = AMDGPU::S_MOV_B32; in SGPRSpillBuilder()
141 MovOpc = AMDGPU::S_MOV_B64; in SGPRSpillBuilder()
216 BuildMI(*MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg); in prepare()
218 BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes); in prepare()
260 auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg) in restore()
969 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 in materializeFrameBaseRegister() local
977 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg) in materializeFrameBaseRegister()
990 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg) in materializeFrameBaseRegister()
H A DSIFrameLowering.cpp1001 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores() local
1002 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1); in emitCSRSpillStores()
1104 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores() local
1105 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1); in emitCSRSpillRestores()
H A DSIWholeQuadMode.cpp1001 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1() local
1002 NewTerm = BuildMI(MBB, &MI, DL, TII->get(MovOpc), Exec).addImm(0); in lowerKillI1()
H A DAMDGPUInstructionSelector.cpp153 unsigned MovOpc = in selectCOPY() local
155 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg) in selectCOPY()
2511 unsigned MovOpc = IsVALU ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32; in selectG_TRUNC() local
2515 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg) in selectG_TRUNC()
H A DSIInstrInfo.cpp5762 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in insertScratchExecCopy() local
5764 auto StoreExecMI = BuildMI(MBB, MBBI, DL, TII->get(MovOpc), Reg) in insertScratchExecCopy()
5766 auto FlipExecMI = BuildMI(MBB, MBBI, DL, TII->get(MovOpc), Exec).addImm(-1); in insertScratchExecCopy()
H A DSIISelLowering.cpp5127 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerWaveReduce() local
5133 BuildMI(BB, MI, DL, TII->get(MovOpc), ExecMask).addReg(ExecReg); in lowerWaveReduce()
5210 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerWaveReduce() local
5217 BuildMI(BB, I, DL, TII->get(MovOpc), LoopIterator).addReg(ExecReg); in lowerWaveReduce()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp245 auto ProcessBLENDWToBLENDD = [&](unsigned MovOpc, unsigned NumElts) -> bool { in processInstruction() argument
246 if (!ST->hasAVX2() || !NewOpcPreferable(MovOpc)) in processInstruction()
257 MI.setDesc(TII->get(MovOpc)); in processInstruction()
265 auto ProcessBLENDToMOV = [&](unsigned MovOpc, unsigned Mask, in processInstruction()
269 if (!OptSize && !NewOpcPreferable(MovOpc)) in processInstruction()
273 MI.setDesc(TII->get(MovOpc)); in processInstruction()
H A DX86IndirectThunks.cpp228 const unsigned MovOpc = Is64Bit ? X86::MOV64mr : X86::MOV32mr; in populateThunk() local
230 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false, in populateThunk()
H A DX86ISelLowering.cpp12798 unsigned MovOpc = 0; in lowerShuffleAsElementInsertion() local
12800 MovOpc = X86ISD::MOVSH; in lowerShuffleAsElementInsertion()
12802 MovOpc = X86ISD::MOVSS; in lowerShuffleAsElementInsertion()
12804 MovOpc = X86ISD::MOVSD; in lowerShuffleAsElementInsertion()
12807 return DAG.getNode(MovOpc, DL, ExtVT, V1, V2); in lowerShuffleAsElementInsertion()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2837 const unsigned MovOpc = in select() local
2839 I.setDesc(TII.get(MovOpc)); in select()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8729 unsigned MovOpc = (WordInt && !Signed) ? PPCISD::MTVSRZ : PPCISD::MTVSRA; in LowerINT_TO_FPDirectMove() local
8730 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()