| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAsmPrinter.cpp | 871 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair() argument
879 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1); in EmitMovFPIntPair()
880 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
888 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams() local
891 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); in EmitSwapFPIntParams()
894 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE); in EmitSwapFPIntParams()
897 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12); in EmitSwapFPIntParams()
898 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE); in EmitSwapFPIntParams()
901 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
904 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE); in EmitSwapFPIntParams()
[all …]
|
| H A D | MipsSEInstrInfo.h | 115 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
|
| H A D | MipsAsmPrinter.h | 99 void EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc,
|
| H A D | MipsSEInstrInfo.cpp | 729 unsigned CvtOpc, unsigned MovOpc, in expandCvtFPInt() argument
731 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); in expandCvtFPInt()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILateBranchLowering.cpp | 39 unsigned MovOpc; member in __anon03252fca0111::SILateBranchLowering
125 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(MovOpc), ExecReg) in expandChainCall()
154 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
200 BuildMI(*EarlyExitBlock, EarlyExitBlock->end(), DL, TII->get(MovOpc), in runOnMachineFunction()
|
| H A D | SIRegisterInfo.cpp | 109 unsigned MovOpc; member
131 MovOpc = AMDGPU::S_MOV_B32; in SGPRSpillBuilder()
135 MovOpc = AMDGPU::S_MOV_B64; in SGPRSpillBuilder()
210 BuildMI(*MBB, MI, DL, TII.get(MovOpc), SavedExecReg).addReg(ExecReg); in prepare()
212 BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg).addImm(VGPRLanes); in prepare()
253 auto I = BuildMI(*MBB, MI, DL, TII.get(MovOpc), ExecReg) in restore()
838 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 in materializeFrameBaseRegister() local
846 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), BaseReg) in materializeFrameBaseRegister()
859 BuildMI(*MBB, Ins, DL, TII->get(MovOpc), FIReg) in materializeFrameBaseRegister()
|
| H A D | SIFrameLowering.cpp | 954 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores() local
955 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1); in emitCSRSpillStores()
1057 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores() local
1058 BuildMI(MBB, MBBI, DL, TII->get(MovOpc), TRI.getExec()).addImm(-1); in emitCSRSpillRestores()
|
| H A D | SIWholeQuadMode.cpp | 991 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1() local
992 NewTerm = BuildMI(MBB, &MI, DL, TII->get(MovOpc), Exec).addImm(0); in lowerKillI1()
|
| H A D | AMDGPUInstructionSelector.cpp | 153 unsigned MovOpc = in selectCOPY() local
155 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg) in selectCOPY()
2269 unsigned MovOpc = IsVALU ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32; in selectG_TRUNC() local
2273 BuildMI(*MBB, I, DL, TII.get(MovOpc), ImmReg) in selectG_TRUNC()
|
| H A D | SIInstrInfo.cpp | 5515 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in insertScratchExecCopy() local
5517 auto StoreExecMI = BuildMI(MBB, MBBI, DL, TII->get(MovOpc), Reg) in insertScratchExecCopy()
5519 auto FlipExecMI = BuildMI(MBB, MBBI, DL, TII->get(MovOpc), Exec).addImm(-1); in insertScratchExecCopy()
|
| H A D | SIISelLowering.cpp | 4894 unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerWaveReduce() local
4902 BuildMI(BB, I, DL, TII->get(MovOpc), LoopIterator).addReg(ExecReg); in lowerWaveReduce()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IndirectThunks.cpp | 234 const unsigned MovOpc = Is64Bit ? X86::MOV64mr : X86::MOV32mr; in populateThunk() local
236 addRegOffset(BuildMI(CallTarget, DebugLoc(), TII->get(MovOpc)), SPReg, false, in populateThunk()
|
| H A D | X86ISelLowering.cpp | 12298 unsigned MovOpc = 0; in lowerShuffleAsElementInsertion() local
12300 MovOpc = X86ISD::MOVSH; in lowerShuffleAsElementInsertion()
12302 MovOpc = X86ISD::MOVSS; in lowerShuffleAsElementInsertion()
12304 MovOpc = X86ISD::MOVSD; in lowerShuffleAsElementInsertion()
12307 return DAG.getNode(MovOpc, DL, ExtVT, V1, V2); in lowerShuffleAsElementInsertion()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2708 const unsigned MovOpc = in select() local
2710 I.setDesc(TII.get(MovOpc)); in select()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8685 unsigned MovOpc = (WordInt && !Signed) ? PPCISD::MTVSRZ : PPCISD::MTVSRA; in LowerINT_TO_FPDirectMove() local
8686 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
|