| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXForwardParams.cpp | 87 static bool eliminateMove(MachineInstr &Mov, const MachineRegisterInfo &MRI, in eliminateMove() argument
92 for (auto &U : MRI.use_instructions(Mov.operands_begin()->getReg())) in eliminateMove()
97 RemoveList.push_back(&Mov); in eliminateMove()
99 const MachineOperand *ParamSymbol = Mov.uses().begin(); in eliminateMove()
|
| H A D | NVPTXISelDAGToDAG.cpp | 2076 SDNode *Mov = in SelectV2I64toI128() local
2082 NewOps[2] = SDValue(Mov, 0); in SelectV2I64toI128()
2107 SDNode *Mov = CurDAG->getMachineNode( in SelectI128toV2I64() local
2112 ReplaceNode(N, Mov); in SelectI128toV2I64()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 90 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction() local
95 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
98 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
|
| H A D | SIPreEmitPeephole.cpp | 96 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVccBranch() local
180 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
183 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
|
| H A D | R600InstrInfo.cpp | 1100 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectWrite() local
1104 setImmOperand(*Mov, R600::OpName::dst_rel, 1); in buildIndirectWrite()
1105 return Mov; in buildIndirectWrite()
1132 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectRead() local
1137 setImmOperand(*Mov, R600::OpName::src0_rel, 1); in buildIndirectRead()
1139 return Mov; in buildIndirectRead()
|
| H A D | SILoadStoreOptimizer.cpp | 1987 MachineInstr *Mov = in createRegOrImm() local
1991 (void)Mov; in createRegOrImm()
1992 LLVM_DEBUG(dbgs() << " "; Mov->dump()); in createRegOrImm()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 952 SDNode *Mov = CurDAG->getMachineNode( in getMaterializedScalarImm32() local
955 return SDValue(Mov, 0); in getMaterializedScalarImm32()
|
| H A D | AMDGPUInstructionSelector.cpp | 1685 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize() local
1691 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize()
|
| H A D | SIISelLowering.cpp | 7535 SDNode *Mov = DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, in getSegmentAperture() local
7540 {SDValue(Mov, 0), DAG.getConstant(32, DL, MVT::i64)})); in getSegmentAperture()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5390 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val); in tryAdvSIMDModImm8() local
5391 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm8()
5392 return &*Mov; in tryAdvSIMDModImm8()
5422 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val).addImm(Shift); in tryAdvSIMDModImm16() local
5423 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm16()
5424 return &*Mov; in tryAdvSIMDModImm16()
5458 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val).addImm(Shift); in tryAdvSIMDModImm32() local
5459 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm32()
5460 return &*Mov; in tryAdvSIMDModImm32()
5478 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val); in tryAdvSIMDModImm64() local
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 847 MachineInstrBuilder Mov; in copyPhysReg() local
865 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); in copyPhysReg()
868 Mov.addReg(Src); in copyPhysReg()
872 addUnpredicatedMveVpredROp(Mov, Dst); in copyPhysReg()
874 Mov = Mov.add(predOps(ARMCC::AL)); in copyPhysReg()
877 Mov = Mov.add(condCodeOp()); in copyPhysReg()
880 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
882 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
|
| H A D | ARMScheduleA9.td | 2153 // A9WriteLfp1-8Mov adds a cycle of latency and FP resource for
2155 def A9WriteLfp#NumAddr#Mov : WriteSequence<
|
| H A D | ARMInstrThumb2.td | 5639 // ARMLowOverheadLoops if possible, or reverted to a Mov if not.
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2189 SDNode *Mov = CurDAG->getMachineNode(Op, DL, {MVT::Untyped, MVT::Other}, Ops); in SelectMultiVectorMove() local
2195 SDValue(Mov, 0))); in SelectMultiVectorMove()
2198 ReplaceUses(SDValue(N, ChainIdx), SDValue(Mov, 1)); in SelectMultiVectorMove()
2225 SDNode *Mov = CurDAG->getMachineNode(Op, DL, {MVT::Untyped, MVT::Other}, Ops); in SelectMultiVectorMoveZ() local
2231 SDValue(Mov, 0))); in SelectMultiVectorMoveZ()
2235 ReplaceUses(SDValue(N, ChainIdx), SDValue(Mov, 1)); in SelectMultiVectorMoveZ()
|
| H A D | AArch64ISelLowering.cpp | 14274 SDValue Mov = in tryAdvSIMDModImm64() local
14276 return DAG.getNode(AArch64ISD::NVCAST, DL, VT, Mov); in tryAdvSIMDModImm64()
14317 SDValue Mov; in tryAdvSIMDModImm32() local
14320 Mov = DAG.getNode(NewOp, DL, MovTy, in tryAdvSIMDModImm32()
14325 Mov = in tryAdvSIMDModImm32()
14329 return DAG.getNode(AArch64ISD::NVCAST, DL, VT, Mov); in tryAdvSIMDModImm32()
14362 SDValue Mov; in tryAdvSIMDModImm16() local
14365 Mov = DAG.getNode(NewOp, DL, MovTy, in tryAdvSIMDModImm16()
14370 Mov = in tryAdvSIMDModImm16()
14374 return DAG.getNode(AArch64ISD::NVCAST, DL, VT, Mov); in tryAdvSIMDModImm16()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8487 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove() local
8489 return DAG.getMergeValues({Mov, Conv.getValue(1)}, dl); in LowerFP_TO_INTDirectMove()
8491 return Mov; in LowerFP_TO_INTDirectMove()
8730 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove() local
8731 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
|