| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 89 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction() local
94 int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(), in runOnMachineFunction()
97 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()
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| H A D | SIPreEmitPeephole.cpp | 94 const unsigned Mov = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in optimizeVccBranch() local
178 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
181 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
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| H A D | R600InstrInfo.cpp | 1109 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectWrite() local
1113 setImmOperand(*Mov, R600::OpName::dst_rel, 1); in buildIndirectWrite()
1114 return Mov; in buildIndirectWrite()
1141 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectRead() local
1146 setImmOperand(*Mov, R600::OpName::src0_rel, 1); in buildIndirectRead()
1148 return Mov; in buildIndirectRead()
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| H A D | SILoadStoreOptimizer.cpp | 1926 MachineInstr *Mov = in createRegOrImm() local
1930 (void)Mov; in createRegOrImm()
1931 LLVM_DEBUG(dbgs() << " "; Mov->dump()); in createRegOrImm()
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| H A D | AMDGPUISelDAGToDAG.cpp | 836 SDNode *Mov = CurDAG->getMachineNode( in getMaterializedScalarImm32() local
839 return SDValue(Mov, 0); in getMaterializedScalarImm32()
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| H A D | AMDGPUInstructionSelector.cpp | 1479 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize() local
1485 auto MIB = BuildMI(*MBB, &I, DL, TII.get(Mov), DstReg); in selectGroupStaticSize()
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| H A D | SIISelLowering.cpp | 6989 SDNode *Mov = DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, in getSegmentAperture() local
6994 {SDValue(Mov, 0), DAG.getConstant(32, DL, MVT::i64)})); in getSegmentAperture()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5253 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val); in tryAdvSIMDModImm8() local
5254 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm8()
5255 return &*Mov; in tryAdvSIMDModImm8()
5285 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val).addImm(Shift); in tryAdvSIMDModImm16() local
5286 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm16()
5287 return &*Mov; in tryAdvSIMDModImm16()
5321 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val).addImm(Shift); in tryAdvSIMDModImm32() local
5322 constrainSelectedInstRegOperands(*Mov, TII, TRI, RBI); in tryAdvSIMDModImm32()
5323 return &*Mov; in tryAdvSIMDModImm32()
5341 auto Mov = Builder.buildInstr(Op, {Dst}, {}).addImm(Val); in tryAdvSIMDModImm64() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1020 MachineInstrBuilder Mov; in copyPhysReg() local
1038 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src); in copyPhysReg()
1041 Mov.addReg(Src); in copyPhysReg()
1045 addUnpredicatedMveVpredROp(Mov, Dst); in copyPhysReg()
1047 Mov = Mov.add(predOps(ARMCC::AL)); in copyPhysReg()
1050 Mov = Mov.add(condCodeOp()); in copyPhysReg()
1053 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1055 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
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| H A D | ARMScheduleA9.td | 2153 // A9WriteLfp1-8Mov adds a cycle of latency and FP resource for
2155 def A9WriteLfp#NumAddr#Mov : WriteSequence<
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| H A D | ARMInstrThumb2.td | 5609 // ARMLowOverheadLoops if possible, or reverted to a Mov if not.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 3836 SDNode *Mov = in SelectV2I64toI128() local
3842 NewOps[2] = SDValue(Mov, 0); in SelectV2I64toI128()
3867 SDNode *Mov = CurDAG->getMachineNode( in SelectI128toV2I64() local
3872 ReplaceNode(N, Mov); in SelectI128toV2I64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2088 SDNode *Mov = CurDAG->getMachineNode(Op, DL, {MVT::Untyped, MVT::Other}, Ops); in SelectMultiVectorMove() local
2094 SDValue(Mov, 0))); in SelectMultiVectorMove()
2097 ReplaceUses(SDValue(N, ChainIdx), SDValue(Mov, 1)); in SelectMultiVectorMove()
2124 SDNode *Mov = CurDAG->getMachineNode(Op, DL, {MVT::Untyped, MVT::Other}, Ops); in SelectMultiVectorMoveZ() local
2130 SDValue(Mov, 0))); in SelectMultiVectorMoveZ()
2134 ReplaceUses(SDValue(N, ChainIdx), SDValue(Mov, 1)); in SelectMultiVectorMoveZ()
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| H A D | AArch64ISelLowering.cpp | 13421 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm64() local
13423 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm64()
13464 SDValue Mov; in tryAdvSIMDModImm32() local
13467 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm32()
13472 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm32()
13476 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm32()
13509 SDValue Mov; in tryAdvSIMDModImm16() local
13512 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm16()
13517 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm16()
13521 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm16()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8421 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove() local
8423 return DAG.getMergeValues({Mov, Conv.getValue(1)}, dl); in LowerFP_TO_INTDirectMove()
8425 return Mov; in LowerFP_TO_INTDirectMove()
8686 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove() local
8687 return convertIntToFP(Op, Mov, DAG, Subtarget); in LowerINT_TO_FPDirectMove()
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