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Searched refs:MemIndexedMode (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1133 LLVM_ABI static const char *getIndexedModeName(ISD::MemIndexedMode AM);
2515 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2528 ISD::MemIndexedMode getAddressingMode() const {
2529 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2549 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2577 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2608 ISD::MemIndexedMode AM, EVT MemVT,
2662 ISD::MemIndexedMode getAddressingMode() const {
2663 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2685 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, bool isExpanding,
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H A DSelectionDAG.h1466 ISD::MemIndexedMode AM);
1468 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
1474 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl,
1484 LLVM_ABI SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
1528 ISD::MemIndexedMode AM);
1531 MachineMemOperand *MMO, ISD::MemIndexedMode AM,
1534 LLVM_ABI SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
1543 getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1555 LLVM_ABI SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
1582 ISD::MemIndexedMode AM);
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H A DISDOpcodes.h1634 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enum
H A DBasicTTIImpl.h195 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) { in getISDIndexedMode()
480 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty) const override { in isIndexedLoadLegal()
485 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty) const override { in isIndexedStoreLegal()
H A DTargetLowering.h3968 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument
3979 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h50 ISD::MemIndexedMode &AM,
54 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DAVRISelDAGToDAG.cpp144 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
H A DAVRISelLowering.cpp1017 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts()
1074 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h130 ISD::MemIndexedMode &AM,
H A DMSP430ISelDAGToDAG.cpp305 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
H A DMSP430ISelLowering.cpp1211 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h400 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
402 ISD::MemIndexedMode &AM,
405 SDValue &Offset, ISD::MemIndexedMode &AM,
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfo.h1755 enum MemIndexedMode { enum
1764 LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1767 LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
H A DTargetTransformInfoImpl.h1034 virtual bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty) const { in isIndexedLoadLegal()
1038 virtual bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty) const { in isIndexedStoreLegal()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h518 ISD::MemIndexedMode &AM,
525 SDValue &Offset, ISD::MemIndexedMode &AM,
H A DARMISelDAGToDAG.cpp830 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg()
866 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre()
886 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm()
965 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset()
1085 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset()
1392 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset()
1444 ISD::MemIndexedMode AM; in SelectT2AddrModeImm7Offset()
1588 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryARMIndexedLoad()
1668 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT1IndexedLoad()
1694 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT2IndexedLoad()
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H A DARMInstrMVE.td7048 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7053 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7132 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
7147 ISD::MemIndexedMode AM = cast<MaskedStoreSDNode>(N)->getAddressingMode();
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h820 ISD::MemIndexedMode &AM,
823 SDValue &Offset, ISD::MemIndexedMode &AM,
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp1339 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode, in isIndexedLoadLegal()
1344 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode, in isIndexedStoreLegal()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9453 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
9477 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad()
9572 ISD::MemIndexedMode AM) { in getIndexedLoad()
9613 MachineMemOperand *MMO, ISD::MemIndexedMode AM, in getStore()
9689 ISD::MemIndexedMode AM) { in getIndexedStore()
9698 ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, in getLoadVP()
9720 SDValue SelectionDAG::getLoadVP(ISD::MemIndexedMode AM, in getLoadVP()
9801 ISD::MemIndexedMode AM) { in getIndexedLoadVP()
9818 ISD::MemIndexedMode AM, bool IsTruncating, in getStoreVP()
9922 ISD::MemIndexedMode AM) { in getIndexedStoreVP()
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H A DSelectionDAGDumper.cpp599 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h306 ISD::MemIndexedMode &AM,
H A DHexagonISelDAGToDAG.cpp461 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad()
570 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1429 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1440 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1481 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1487 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h859 ISD::MemIndexedMode &AM,

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