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Searched refs:Matrix (Results 1 – 25 of 81) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/PBQP/
H A DMath.h121 class Matrix {
123 friend hash_code hash_value(const Matrix &);
127 Matrix(unsigned Rows, unsigned Cols) : in Matrix() function
133 Matrix(unsigned Rows, unsigned Cols, PBQPNum InitVal) in Matrix() function
140 Matrix(const Matrix &M) in Matrix() function
147 Matrix(Matrix &&M) in Matrix() function
153 bool operator==(const Matrix &M) const {
205 Matrix transpose() const { in transpose()
207 Matrix M(Cols, Rows); in transpose()
215 Matrix& operator+=(const Matrix &M) {
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H A DReductionRules.h34 using Matrix = typename GraphT::Matrix; in applyR1() local
43 const Matrix &ECosts = G.getEdgeCosts(EId); in applyR1()
78 using Matrix = typename GraphT::Matrix; in applyR2() local
96 const Matrix *YXECosts = FlipEdge1 ? in applyR2()
97 new Matrix(G.getEdgeCosts(YXEId).transpose()) : in applyR2()
100 const Matrix *ZXECosts = FlipEdge2 ? in applyR2()
101 new Matrix(G.getEdgeCosts(ZXEId).transpose()) : in applyR2()
134 const Matrix &YZECosts = G.getEdgeCosts(YZEId); in applyR2()
182 using Matrix = typename GraphT::Matrix; in backpropagate() local
203 const Matrix& edgeCosts = G.getEdgeCosts(EId); in backpropagate()
H A DGraph.h54 using Matrix = typename SolverT::Matrix; variable
530 const Matrix& getEdgeCosts(EdgeId EId) const { in getEdgeCosts()
H A DCostAllocator.h114 using Matrix = MatrixT; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp319 ArrayRef<Instruction *> Matrix, in interleave8bitStride4VF8() argument
345 Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow); in interleave8bitStride4VF8()
347 Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow); in interleave8bitStride4VF8()
359 ArrayRef<Instruction *> Matrix, SmallVectorImpl<Value *> &TransposedMatrix, in interleave8bitStride4() argument
397 IntrVec[0] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow); in interleave8bitStride4()
398 IntrVec[1] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh); in interleave8bitStride4()
399 IntrVec[2] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow); in interleave8bitStride4()
400 IntrVec[3] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh); in interleave8bitStride4()
685 ArrayRef<Instruction *> Matrix, in transpose_4x4() argument
687 assert(Matrix.size() == 4 && "Invalid matrix size"); in transpose_4x4()
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H A DX86RegisterInfo.h178 const LiveRegMatrix *Matrix) const override;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp61 if (NumRegUnits != Matrix.size()) in runOnMachineFunction()
63 Matrix.init(LIUAlloc, NumRegUnits); in runOnMachineFunction()
71 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) { in releaseMemory()
72 Matrix[i].clear(); in releaseMemory()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
130 Matrix[Unit].extract(VirtReg, Range); in unassign()
140 if (!Matrix[Unit].empty()) in isPhysRegUsed()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
233 Q.reset(UserTag, LR, Matrix[Unit]); in checkInterference()
243 if ((VRegInterval = Matrix[Unit].getOneVReg())) in getOneVReg()
H A DRegAllocBasic.cpp149 Matrix->unassign(LI); in INITIALIZE_PASS_DEPENDENCY()
167 Matrix->unassign(LI); in LRE_WillShrinkVirtReg()
215 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in spillInterferences()
234 Matrix->unassign(*Spill); in spillInterferences()
262 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit()
266 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
287 assert(!Matrix->checkInterference(VirtReg, PhysReg) && in selectOrSplit()
H A DAllocationOrder.cpp31 const LiveRegMatrix *Matrix) { in create() argument
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
H A DRegAllocGreedy.cpp237 Matrix->unassign(LI); in LRE_CanEraseVirtReg()
255 Matrix->unassign(LI); in LRE_WillShrinkVirtReg()
404 if (!Matrix->checkInterference(VirtReg, *I)) { in tryAssign()
459 LiveIntervalUnion::Query SubQ(VirtReg, Matrix->getLiveUnions()[Unit]); in canReassign()
464 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) { in canReassign()
495 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in evictInterference()
510 Matrix->unassign(*Intf); in evictInterference()
527 return !Matrix->isPhysRegUsed(PhysReg); in isUnusedCalleeSavedReg()
1506 if (!Matrix->query(const_cast<LiveInterval &>(SA->getParent()), Unit) in calcGapWeights()
1518 Matrix->getLiveUnions()[Unit].find(StartIdx); in calcGapWeights()
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H A DRegAllocBase.cpp64 Matrix = &mat; in init()
101 Matrix->invalidateVirtRegs(); in allocatePhysRegs()
142 Matrix->assign(*VirtReg, AvailablePhysReg); in allocatePhysRegs()
H A DRegAllocEvictionAdvisor.cpp128 : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()), in RegAllocEvictionAdvisor()
190 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterferenceBasedOnCost()
206 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in canEvictInterferenceBasedOnCost()
H A DRegAllocBase.h70 LiveRegMatrix *Matrix = nullptr; variable
H A DAllocationOrder.h86 const LiveRegMatrix *Matrix);
H A DRegAllocEvictionAdvisor.h139 LiveRegMatrix *const Matrix; variable
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DMatrixBuilder.h89 CallInst *CreateColumnMajorStore(Value *Matrix, Value *Ptr, Align Alignment,
93 Value *Ops[] = {Matrix, Ptr,
96 Type *OverloadedTypes[] = {Matrix->getType(), Stride->getType()};
110 CallInst *CreateMatrixTranspose(Value *Matrix, unsigned Rows,
112 auto *OpType = cast<VectorType>(Matrix->getType());
117 Value *Ops[] = {Matrix, B.getInt32(Rows), B.getInt32(Columns)};
146 Value *CreateMatrixInsert(Value *Matrix, Value *NewVal, Value *RowIdx, in CreateMatrixInsert() argument
149 Matrix, NewVal, in CreateMatrixInsert()
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Datmel-matrix.txt1 * Device tree bindings for Atmel Bus Matrix
3 The Bus Matrix registers are used to configure Atmel SoCs internal bus
18 - reg: Contains offset/length value of the Bus Matrix
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp43 LiveRegMatrix *Matrix; member in __anonf07969e70111::SIPreAllocateWWMRegs
107 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
108 Matrix->assign(LI, PhysReg); in processDef()
197 Matrix = &getAnalysis<LiveRegMatrix>(); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h50 LiveIntervalUnion::Array Matrix; variable
157 LiveIntervalUnion *getLiveUnions() { return &Matrix[0]; } in getLiveUnions()
H A DRegAllocPBQP.h55 MatrixMetadata(const Matrix& M) in MatrixMetadata()
276 using RawMatrix = PBQP::Matrix;
278 using Matrix = RAMatrix; variable
279 using CostAllocator = PBQP::PoolCostAllocator<Vector, Matrix>;
328 void handleUpdateCosts(EdgeId EId, const Matrix& NewCosts) { in handleUpdateCosts()
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-matrix.dts3 * Device Tree file for Marvell Armada XP Matrix board
14 model = "Marvell Armada XP Matrix Board";
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td163 "Enable Matrix Multiply Int8 Extension">;
167 "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
171 "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
410 "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
413 "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME]>;
416 "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME]>;
426 "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
454 "Enable Scalable Matrix Extension 2.1 instructions", [FeatureSME2]>;
509 "Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
512 "Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h152 const LiveRegMatrix *Matrix) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td1460 // 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands
1466 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands
1479 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands
1505 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands
1518 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands
1545 // 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands
1552 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h131 const LiveRegMatrix *Matrix) const override;

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