| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 307 unsigned &MaskLen) { in isShiftedMask_32() argument
311 MaskLen = llvm::popcount(Value); in isShiftedMask_32()
320 unsigned &MaskLen) { in isShiftedMask_64() argument
324 MaskLen = llvm::popcount(Value); in isShiftedMask_64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 1878 const unsigned MaskLen = LastElt - FirstElt + 1; in simplifyAMDGCNLaneIntrinsicDemanded() local
1881 if (MaskLen == OldNumElts && MaskLen != 1) in simplifyAMDGCNLaneIntrinsicDemanded()
1885 Type *NewVT = MaskLen == 1 ? EltTy : FixedVectorType::get(EltTy, MaskLen); in simplifyAMDGCNLaneIntrinsicDemanded()
1903 if (MaskLen == 1) { in simplifyAMDGCNLaneIntrinsicDemanded()
1913 SmallVector<int> ExtractMask(MaskLen, -1); in simplifyAMDGCNLaneIntrinsicDemanded()
1914 for (unsigned I = 0; I != MaskLen; ++I) { in simplifyAMDGCNLaneIntrinsicDemanded()
1925 for (unsigned I = 0; I != MaskLen; ++I) { in simplifyAMDGCNLaneIntrinsicDemanded()
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| H A D | AMDGPUISelLowering.cpp | 4278 unsigned MaskIdx, MaskLen; in performSrlCombine() local
4279 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 522 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
524 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
530 MaskLen = Ones; in isShiftedMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 633 unsigned MaskIdx, MaskLen;
635 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
636 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
641 unsigned MaskIdx, MaskLen;
643 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
644 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
645 return CurDAG->getTargetConstant(MaskIdx + MaskLen - 1, SDLoc(N),
651 unsigned MaskIdx, MaskLen;
653 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
654 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
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| H A D | LoongArchISelLowering.cpp | 4489 unsigned MaskIdx, MaskLen; in performSRLCombine() local
4496 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
4504 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
4507 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
4862 unsigned MaskIdx, MaskLen; in performORCombine() local
4865 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
4867 CNShamt->getZExtValue() + MaskLen <= ValBits) { in performORCombine()
4874 DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT), in performORCombine()
4889 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
4898 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2224 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2225 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2268 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2269 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
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| H A D | X86ISelDAGToDAG.cpp | 2247 unsigned MaskIdx, MaskLen; in foldMaskAndShiftToScale() local
2248 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskAndShiftToScale()
2250 unsigned MaskLZ = 64 - (MaskIdx + MaskLen); in foldMaskAndShiftToScale()
2346 unsigned MaskIdx, MaskLen; in foldMaskedShiftToBEXTR() local
2347 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskedShiftToBEXTR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1080 unsigned MaskLen = SM.Mask.size(); in getOutputSegmentMap() local
1081 assert(MaskLen % SegLen == 0); in getOutputSegmentMap()
1082 SmallVector<unsigned, 4> Map(MaskLen / SegLen); in getOutputSegmentMap()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 756 unsigned LowZBits, MaskLen; in SelectShiftedRegisterFromAnd() local
757 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
767 if (LowZBits <= ShiftAmtC || (BitWidth != LowZBits + MaskLen)) in SelectShiftedRegisterFromAnd()
782 if (LHSOpcode == ISD::SRA && (BitWidth != (LowZBits + MaskLen))) in SelectShiftedRegisterFromAnd()
786 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) in SelectShiftedRegisterFromAnd()
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| H A D | AArch64ISelLowering.cpp | 16685 unsigned MaskLen = NumElts * Factor; in createTblShuffleMask() local
16688 Mask.resize(MaskLen, NumElts); in createTblShuffleMask()
16691 for (unsigned I = IsLittleEndian ? 0 : Factor - 1; I < MaskLen; I += Factor) in createTblShuffleMask()
17959 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
17960 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
17964 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
17965 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13925 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13926 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13930 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13931 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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