| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 306 unsigned &MaskLen) { in isShiftedMask_32() argument
310 MaskLen = llvm::popcount(Value); in isShiftedMask_32()
319 unsigned &MaskLen) { in isShiftedMask_64() argument
323 MaskLen = llvm::popcount(Value); in isShiftedMask_64()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 502 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() argument
504 return isShiftedMask_64(U.VAL, MaskIdx, MaskLen); in isShiftedMask()
510 MaskLen = Ones; in isShiftedMask()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 594 unsigned MaskIdx, MaskLen;
596 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
597 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
602 unsigned MaskIdx, MaskLen;
604 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
605 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
606 return CurDAG->getTargetConstant(MaskIdx + MaskLen - 1, SDLoc(N),
612 unsigned MaskIdx, MaskLen;
614 ? llvm::isShiftedMask_32(~Imm, MaskIdx, MaskLen)
615 : llvm::isShiftedMask_64(~Imm, MaskIdx, MaskLen);
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| H A D | LoongArchISelLowering.cpp | 3206 unsigned MaskIdx, MaskLen; in performSRLCombine() local
3213 !isShiftedMask_64(CN->getZExtValue(), MaskIdx, MaskLen)) in performSRLCombine()
3221 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
3224 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performSRLCombine()
3367 unsigned MaskIdx, MaskLen; in performORCombine() local
3370 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
3372 CNShamt->getZExtValue() + MaskLen <= ValBits) { in performORCombine()
3379 DAG.getConstant(Shamt + MaskLen - 1, DL, GRLenVT), in performORCombine()
3394 isShiftedMask_64(CNMask->getZExtValue(), MaskIdx, MaskLen) && in performORCombine()
3403 DAG.getConstant(MaskIdx + MaskLen - 1, DL, GRLenVT), in performORCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2216 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2217 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2260 unsigned MaskIdx, MaskLen; in instCombineIntrinsic() local
2261 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
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| H A D | X86ISelDAGToDAG.cpp | 2189 unsigned MaskIdx, MaskLen; in foldMaskAndShiftToScale() local
2190 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskAndShiftToScale()
2192 unsigned MaskLZ = 64 - (MaskIdx + MaskLen); in foldMaskAndShiftToScale()
2288 unsigned MaskIdx, MaskLen; in foldMaskedShiftToBEXTR() local
2289 if (!isShiftedMask_64(Mask, MaskIdx, MaskLen)) in foldMaskedShiftToBEXTR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1086 unsigned MaskLen = SM.Mask.size(); in getOutputSegmentMap() local
1087 assert(MaskLen % SegLen == 0); in getOutputSegmentMap()
1088 SmallVector<unsigned, 4> Map(MaskLen / SegLen); in getOutputSegmentMap()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 752 unsigned LowZBits, MaskLen; in SelectShiftedRegisterFromAnd() local
753 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
763 if (LowZBits <= ShiftAmtC || (BitWidth != LowZBits + MaskLen)) in SelectShiftedRegisterFromAnd()
778 if (LHSOpcode == ISD::SRA && (BitWidth != (LowZBits + MaskLen))) in SelectShiftedRegisterFromAnd()
782 if (LHSOpcode == ISD::SRL && (BitWidth > (NewShiftC + MaskLen))) in SelectShiftedRegisterFromAnd()
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| H A D | AArch64ISelLowering.cpp | 16296 unsigned MaskLen = NumElts * Factor; in createTblShuffleMask() local
16299 Mask.resize(MaskLen, NumElts); in createTblShuffleMask()
16302 for (unsigned I = IsLittleEndian ? 0 : Factor - 1; I < MaskLen; I += Factor) in createTblShuffleMask()
17530 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
17531 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
17535 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
17536 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4108 unsigned MaskIdx, MaskLen; in performSrlCombine() local
4109 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13850 unsigned MaskIdx, MaskLen; in isDesirableToCommuteXorWithShift() local
13851 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
13855 return MaskIdx == ShiftAmt && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
13856 return MaskIdx == 0 && MaskLen == (BitWidth - ShiftAmt); in isDesirableToCommuteXorWithShift()
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