| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoM.td | 39 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
77 def : PatGprGpr<mulhu, MULHU>;
117 // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
120 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
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| H A D | RISCVISelDAGToDAG.cpp | 1724 SDNode *MULHU = CurDAG->getMachineNode(RISCV::MULHU, DL, VT, in Select() local
1726 ReplaceNode(Node, MULHU); in Select()
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| H A D | RISCVTargetTransformInfo.cpp | 2444 case ISD::MULHU: in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 202 case ISD::MULHU: { in trySelect()
203 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
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| H A D | MipsSEISelLowering.cpp | 217 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
228 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
270 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
317 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
495 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 159 R_TYPE_INST(MULHU);
279 SRLW, SRAW, MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU, MULW, DIVW,
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| H A D | EmulateInstructionRISCV.cpp | 473 {"MULHU", 0xFE00707F, 0x2003033, DecodeRType<MULHU>},
1010 bool operator()(MULHU inst) { in operator ()()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 695 MULHU, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 498 setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand); in AMDGPUTargetLowering()
500 setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand); in AMDGPUTargetLowering()
523 ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, in AMDGPUTargetLowering()
630 ISD::MULHU, ISD::MULHS, in AMDGPUTargetLowering()
2154 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
2167 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
2178 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2320 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2323 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
5382 case ISD::MULHU: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 230 setOperationAction(ISD::MULHU, T, Legal); in initializeHVXLowering()
307 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
342 setOperationAction(ISD::MULHU, WordV, Custom); // -> _LOHI in initializeHVXLowering()
1925 if (Opc == ISD::MULHU) in LowerHvxMulh()
3209 case ISD::MULHU: in LowerHvxOperation()
3259 case ISD::MULHU: return LowerHvxMulh(Op, DAG); in LowerHvxOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 122 setOperationAction(ISD::MULHU, MVT::i8, Promote); in MSP430TargetLowering()
127 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 735 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
1286 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1971 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 141 setOperationAction(ISD::MULHU, MVT::i32, Legal); in XtensaTargetLowering()
144 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 142 setOperationAction(ISD::MULHU, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 276 case ISD::MULHU: return "mulhu"; in getOperationName()
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| H A D | TargetLowering.cpp | 3798 case ISD::MULHU: in SimplifyDemandedVectorElts()
6799 if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization)) in BuildUDIV()
6800 return DAG.getNode(ISD::MULHU, dl, VT, X, Y); in BuildUDIV()
7773 isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL_LOHI()
7799 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); in expandMUL_LOHI()
8004 if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) && in expandDIVREMByConstant()
11193 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; in expandFixedPointMul()
11493 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in expandMULO()
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| H A D | LegalizeDAG.cpp | 3928 case ISD::MULHU: in ExpandNode()
3931 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3946 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3984 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); in ExpandNode()
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| H A D | LegalizeVectorOps.cpp | 358 case ISD::MULHU: in LegalizeOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 114 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 76 setOperationAction(ISD::MULHU, MVT::i32, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 112 setOperationAction(ISD::MULHU, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 225 setOperationAction(ISD::MULHU, VT, Expand); in SystemZTargetLowering()
264 setOperationAction(ISD::MULHU, MVT::i128, Expand); in SystemZTargetLowering()
275 setOperationAction(ISD::MULHU, MVT::i64, Custom); in SystemZTargetLowering()
454 setOperationAction(ISD::MULHU, VT, Legal); in SystemZTargetLowering()
5430 return DAG.getNode(ISD::MULHU, SDLoc(Op), Op.getValueType(), in lowerINTRINSIC_WO_CHAIN()
7048 case ISD::MULHU: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1826 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1841 setOperationAction(ISD::MULHU, MVT::i64, in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 71 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 184 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
|