| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoM.td | 34 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
72 def : PatGprGpr<mulhu, MULHU>;
112 // inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
115 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
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| H A D | RISCVISelDAGToDAG.cpp | 1522 SDNode *MULHU = CurDAG->getMachineNode(RISCV::MULHU, DL, VT, in Select() local
1524 ReplaceNode(Node, MULHU); in Select()
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| H A D | RISCVTargetTransformInfo.cpp | 1729 case ISD::MULHU: in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 211 case ISD::MULHU: { in trySelect()
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
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| H A D | MipsSEISelLowering.cpp | 178 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
189 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
231 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
278 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
456 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 159 R_TYPE_INST(MULHU);
279 SRLW, SRAW, MUL, MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU, MULW, DIVW,
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| H A D | EmulateInstructionRISCV.cpp | 473 {"MULHU", 0xFE00707F, 0x2003033, DecodeRType<MULHU>},
1009 bool operator()(MULHU inst) { in operator ()()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 673 MULHU, enumerator
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| H A D | TargetLowering.h | 2889 case ISD::MULHU: in isCommutativeBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 485 setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand); in AMDGPUTargetLowering()
487 setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand); in AMDGPUTargetLowering()
510 ISD::FP_TO_UINT, ISD::MUL, ISD::MULHU, in AMDGPUTargetLowering()
617 ISD::MULHU, ISD::MULHS, in AMDGPUTargetLowering()
2097 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
2110 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
2121 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2263 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2266 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
5149 case ISD::MULHU: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 226 setOperationAction(ISD::MULHU, T, Legal); in initializeHVXLowering()
301 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
336 setOperationAction(ISD::MULHU, WordV, Custom); // -> _LOHI in initializeHVXLowering()
1910 if (Opc == ISD::MULHU) in LowerHvxMulh()
3172 case ISD::MULHU: in LowerHvxOperation()
3222 case ISD::MULHU: return LowerHvxMulh(Op, DAG); in LowerHvxOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 406 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
945 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1554 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 123 setOperationAction(ISD::MULHU, MVT::i8, Promote); in MSP430TargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 141 setOperationAction(ISD::MULHU, MVT::i32, Legal); in ARCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 259 case ISD::MULHU: return "mulhu"; in getOperationName()
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| H A D | TargetLowering.cpp | 3644 case ISD::MULHU: in SimplifyDemandedVectorElts()
6578 if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization)) in BuildUDIV()
6579 return DAG.getNode(ISD::MULHU, dl, VT, X, Y); in BuildUDIV()
7554 isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL_LOHI()
7580 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); in expandMUL_LOHI()
7785 if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) && in expandDIVREMByConstant()
10694 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; in expandFixedPointMul()
10991 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in expandMULO()
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| H A D | LegalizeDAG.cpp | 3789 case ISD::MULHU: in ExpandNode()
3792 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; in ExpandNode()
3807 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3845 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); in ExpandNode()
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| H A D | LegalizeVectorOps.cpp | 347 case ISD::MULHU: in LegalizeOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 106 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 76 setOperationAction(ISD::MULHU, MVT::i32, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 114 setOperationAction(ISD::MULHU, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1832 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1855 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 99 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 639 setOperationAction(ISD::MULHU, MVT::i32, Expand); in AArch64TargetLowering()
1328 setOperationAction(ISD::MULHU, VT, Legal); in AArch64TargetLowering()
1331 setOperationAction(ISD::MULHU, VT, Expand); in AArch64TargetLowering()
1444 setOperationAction(ISD::MULHU, VT, Custom); in AArch64TargetLowering()
1716 setOperationAction(ISD::MULHU, MVT::v1i64, Custom); in AArch64TargetLowering()
1717 setOperationAction(ISD::MULHU, MVT::v2i64, Custom); in AArch64TargetLowering()
1740 setOperationAction(ISD::MULHU, VT, Custom); in AArch64TargetLowering()
2084 setOperationAction(ISD::MULHU, VT, Default); in addTypeForFixedLengthSVE()
4043 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
6928 case ISD::MULHU: in LowerOperation()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 185 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
|