| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 201 case ISD::MULHS: in trySelect()
|
| H A D | MipsSEISelLowering.cpp | 216 setOperationAction(ISD::MULHS, MVT::i32, Custom); in MipsSETargetLowering()
227 setOperationAction(ISD::MULHS, MVT::i64, Custom); in MipsSETargetLowering()
269 setOperationAction(ISD::MULHS, MVT::i32, Legal); in MipsSETargetLowering()
316 setOperationAction(ISD::MULHS, MVT::i64, Legal); in MipsSETargetLowering()
494 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 696 MULHS, enumerator
|
| H A D | TargetLowering.h | 2974 case ISD::MULHS: in isCommutativeBinOp()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 229 setOperationAction(ISD::MULHS, T, Legal); in initializeHVXLowering()
306 setOperationAction(ISD::MULHS, T, Custom); in initializeHVXLowering()
341 setOperationAction(ISD::MULHS, WordV, Custom); // -> _LOHI in initializeHVXLowering()
1927 if (Opc == ISD::MULHS) in LowerHvxMulh()
3208 case ISD::MULHS: in LowerHvxOperation()
3258 case ISD::MULHS: in LowerHvxOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 121 setOperationAction(ISD::MULHS, MVT::i8, Promote); in MSP430TargetLowering()
126 setOperationAction(ISD::MULHS, MVT::i16, Expand); in MSP430TargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 734 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
1285 X86_INTRINSIC_DATA(avx512_pmulh_w_512, INTR_TYPE_2OP, ISD::MULHS, 0),
1970 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 142 setOperationAction(ISD::MULHS, MVT::i32, Legal); in XtensaTargetLowering()
145 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XtensaTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 141 setOperationAction(ISD::MULHS, MVT::i32, Legal); in ARCTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 277 case ISD::MULHS: return "mulhs"; in getOperationName()
|
| H A D | TargetLowering.cpp | 3799 case ISD::MULHS: in SimplifyDemandedVectorElts()
6610 if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization)) in BuildSDIV()
6611 return DAG.getNode(ISD::MULHS, dl, VT, X, Y); in BuildSDIV()
7771 isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL_LOHI()
7799 Hi = DAG.getNode(Signed ? ISD::MULHS : ISD::MULHU, dl, HiLoVT, L, R); in expandMUL_LOHI()
11193 unsigned HiOp = Signed ? ISD::MULHS : ISD::MULHU; in expandFixedPointMul()
11494 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in expandMULO()
|
| H A D | LegalizeDAG.cpp | 3929 case ISD::MULHS: { in ExpandNode()
3946 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; in ExpandNode()
3983 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); in ExpandNode()
|
| H A D | LegalizeVectorOps.cpp | 357 case ISD::MULHS: in LegalizeOp()
|
| H A D | LegalizeVectorTypes.cpp | 182 case ISD::MULHS: in ScalarizeVectorResult()
1292 case ISD::MULHS: in SplitVectorResult()
4737 case ISD::MULHS: in WidenVectorResult()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 115 setOperationAction(ISD::MULHS, VT, Expand); in BPFTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 498 setOperationAction({ISD::MULHU, ISD::MULHS}, MVT::i16, Expand); in AMDGPUTargetLowering()
500 setOperationAction({ISD::MUL, ISD::MULHU, ISD::MULHS}, MVT::i64, Expand); in AMDGPUTargetLowering()
524 ISD::MULHS, ISD::OR, ISD::SHL, in AMDGPUTargetLowering()
630 ISD::MULHU, ISD::MULHS, in AMDGPUTargetLowering()
5380 case ISD::MULHS: in PerformDAGCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 75 setOperationAction(ISD::MULHS, MVT::i32, Expand); in CSKYTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 113 setOperationAction(ISD::MULHS, MVT::i32, Expand); in LanaiTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 224 setOperationAction(ISD::MULHS, VT, Expand); in SystemZTargetLowering()
263 setOperationAction(ISD::MULHS, MVT::i128, Expand); in SystemZTargetLowering()
274 setOperationAction(ISD::MULHS, MVT::i64, Custom); in SystemZTargetLowering()
453 setOperationAction(ISD::MULHS, VT, Legal); in SystemZTargetLowering()
5423 return DAG.getNode(ISD::MULHS, SDLoc(Op), Op.getValueType(), in lowerINTRINSIC_WO_CHAIN()
7046 case ISD::MULHS: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1827 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1843 setOperationAction(ISD::MULHS, MVT::i64, in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 70 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 183 setOperationAction(ISD::MULHS, VT, Expand); in AVRTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 2443 case ISD::MULHS: in getArithmeticInstrCost()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 654 setOperationAction(ISD::MULHS, MVT::i32, Expand); in AArch64TargetLowering()
1382 setOperationAction(ISD::MULHS, VT, Legal); in AArch64TargetLowering()
1385 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
1535 setOperationAction(ISD::MULHS, VT, Custom); in AArch64TargetLowering()
1843 setOperationAction(ISD::MULHS, MVT::v1i64, Custom); in AArch64TargetLowering()
1844 setOperationAction(ISD::MULHS, MVT::v2i64, Custom); in AArch64TargetLowering()
1868 setOperationAction(ISD::MULHS, VT, Custom); in AArch64TargetLowering()
2320 setOperationAction(ISD::MULHS, VT, Default); in addTypeForFixedLengthSVE()
4047 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
7394 case ISD::MULHS: in LowerOperation()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 643 ISD::MUL, ISD::MULHS, ISD::MULHU, ISD::PARITY, in NVPTXTargetLowering()
812 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SRA, ISD::SRL, ISD::MULHS, in NVPTXTargetLowering()
|