Searched refs:MTC1_D64 (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrFPU.td | 55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
566 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
946 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
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| H A D | MipsISelLowering.h | 107 MTC1_D64, enumerator
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| H A D | MipsInstrInfo.cpp | 636 case Mips::MTC1_D64: in HasFPUDelaySlot()
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| H A D | MipsScheduleP5600.td | 564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| H A D | MipsSEISelLowering.cpp | 416 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
3770 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
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| H A D | MipsScheduleGeneric.td | 872 MFHC1_D64, MTC1, MTC1_D64,
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| H A D | MipsISelLowering.cpp | 197 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; in getTargetNodeName()
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