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Searched refs:MTC1_D64 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>;
566 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
946 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
H A DMipsISelLowering.h107 MTC1_D64, enumerator
H A DMipsInstrInfo.cpp659 case Mips::MTC1_D64: in HasFPUDelaySlot()
H A DMipsScheduleI6400.td118 MFHC1_D32, MFHC1_D64, MTC1, MTC1_D64, MTHC1_D32, MTHC1_D64,
H A DMipsScheduleP5600.td564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
H A DMipsSEISelLowering.cpp455 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
3831 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
H A DMipsScheduleGeneric.td872 MFHC1_D64, MTC1, MTC1_D64,
H A DMipsISelLowering.cpp195 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; in getTargetNodeName()