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Searched refs:MTC1 (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp122 Opc = Mips::MTC1; in copyPhysReg()
418 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
422 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
429 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
799 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
H A DMipsInstructionSelector.cpp598 MachineInstrBuilder MTC1 = in select() local
599 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
600 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
H A DMipsAsmPrinter.cpp848 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
888 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
H A DMipsInstrFPU.td564 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
937 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
938 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
H A DMipsInstrInfo.cpp634 case Mips::MTC1: in HasFPUDelaySlot()
H A DMipsScheduleP5600.td564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
H A DMipsFastISel.cpp392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
H A DMipsScheduleGeneric.td872 MFHC1_D64, MTC1, MTC1_D64,
H A DMipsSEISelLowering.cpp3770 : (IsFGR64onMips32 ? Mips::MTC1_D64 : Mips::MTC1); in emitFPEXTEND_PSEUDO()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3470 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3600 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3603 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3604 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()