| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 121 unsigned MOVi32imm; member
333 STORE_OPCODE(MOVi32imm, MOVi32imm); in OpcodeCache()
725 TII.get(Opcodes.MOVi32imm), Offset); in selectGlobal()
749 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
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| H A D | ARMInstrInfo.cpp | 120 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12); in expandLoadStackGuard()
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| H A D | ARMScheduleR52.td | 219 (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi", "t2MOVi")>;
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| H A D | ARMScheduleSwift.td | 166 (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm",
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| H A D | ARMExpandPseudoInsts.cpp | 1074 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
2742 case ARM::MOVi32imm: in ExpandMI()
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| H A D | ARMInstrInfo.td | 6007 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
6047 (MOVi32imm tglobaltlsaddr :$dst)>,
6068 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
6070 def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>,
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| H A D | ARMFastISel.cpp | 553 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; in ARMMaterializeGV()
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| H A D | ARMScheduleA9.td | 2539 def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm")>;
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| H A D | ARMBaseInstrInfo.cpp | 3317 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm && in foldImmediate()
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| H A D | ARMISelLowering.cpp | 11588 BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm), in EmitStructByval()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MIPeepholeOpt.cpp | 471 if (MovMI->getOpcode() != AArch64::MOVi32imm && in checkMovImmInstr()
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| H A D | AArch64InstrInfo.td | 2191 def MOVi32imm
2201 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
2225 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
2228 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
2241 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
2445 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
2447 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
2450 (MOVi32imm (trunc_imm imm:$C)), XZR)>;
2453 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
2455 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
[all …]
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| H A D | SVEInstrFormats.td | 5734 …(!cast<Instruction>(NAME # "_B") (i32 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("tr…
5736 …(!cast<Instruction>(NAME # "_H") (i32 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("tr…
5738 (!cast<Instruction>(NAME # "_S") (i32 0), (!cast<Instruction>("MOVi32imm") $imm))>;
5742 …ion>(NAME # "_D") (i64 0), (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeX…
5746 …(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXFo…
5748 …(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXF…
5750 … (!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, (!cast<Instruction>("MOVi32imm") $imm))>;
5754 …E # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeX…
5840 …(!cast<Instruction>(NAME # "_B") GPR32:$Rn, (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("…
5842 …(!cast<Instruction>(NAME # "_H") GPR32:$Rn, (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("…
[all …]
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| H A D | AArch64ExpandPseudoInsts.cpp | 1457 case AArch64::MOVi32imm: in expandMI()
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| H A D | AArch64SVEInstrInfo.td | 862 (DUP_ZR_H (MOVi32imm (bitcast_fpimm_to_i32 f16:$val)))>;
864 (DUP_ZR_H (MOVi32imm (bitcast_fpimm_to_i32 f16:$val)))>;
866 (DUP_ZR_H (MOVi32imm (bitcast_fpimm_to_i32 f16:$val)))>;
868 (DUP_ZR_S (MOVi32imm (bitcast_fpimm_to_i32 f32:$val)))>;
870 (DUP_ZR_S (MOVi32imm (bitcast_fpimm_to_i32 f32:$val)))>;
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| H A D | AArch64SchedFalkorDetails.td | 1236 def : InstRW<[FalkorWr_1XYZ_0cyc], (instrs MOVi32imm, MOVi64imm)>; // imm fwd (approximation)
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| H A D | AArch64FastISel.cpp | 413 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
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| H A D | AArch64ISelDAGToDAG.cpp | 3316 unsigned MOVIOpc = VT == MVT::i32 ? AArch64::MOVi32imm : AArch64::MOVi64imm; in tryBitfieldInsertOpFromOrAndImm()
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| H A D | AArch64InstrInfo.cpp | 923 case AArch64::MOVi32imm: in isAsCheapAsAMove()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2709 DefSize == 64 ? AArch64::MOVi64imm : AArch64::MOVi32imm; in select()
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